Search

Vinh P Nguyen

Examiner (ID: 8115, Phone: (571)272-1964 , Office: P/2867 )

Most Active Art Unit
2858
Art Unit(s)
2858, 2899, 2213, 3621, 2607, 2867, 2829, 2731
Total Applications
3600
Issued Applications
3079
Pending Applications
119
Abandoned Applications
402

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17583118 [patent_doc_number] => 20220139973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/574312 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574312
Solid-state imaging device, method of manufacturing the same, and electronic equipment Jan 11, 2022 Issued
Array ( [id] => 17566862 [patent_doc_number] => 20220131011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/571561 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571561
Semiconductor device and method of manufacturing the same Jan 9, 2022 Issued
Array ( [id] => 17566859 [patent_doc_number] => 20220131008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/569952 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569952 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569952
Integrated circuit device Jan 5, 2022 Issued
Array ( [id] => 17566813 [patent_doc_number] => 20220130962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME [patent_app_type] => utility [patent_app_number] => 17/569376 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569376
NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME Jan 4, 2022 Pending
Array ( [id] => 18440246 [patent_doc_number] => 20230187541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => CROSS BAR VERTICAL FETS [patent_app_type] => utility [patent_app_number] => 17/644528 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644528
CROSS BAR VERTICAL FETS Dec 14, 2021 Pending
Array ( [id] => 17506679 [patent_doc_number] => 20220099782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SYNCHRONIZATION OF UNSTABLE SIGNAL SOURCES FOR USE IN A PHASE STABLE INSTRUMENT [patent_app_type] => utility [patent_app_number] => 17/548381 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548381
Synchronization of unstable signal sources for use in a phase stable instrument Dec 9, 2021 Issued
Array ( [id] => 17676608 [patent_doc_number] => 20220189775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => METHOD OF FORMING STRUCTURES FOR THRESHOLD VOLTAGE CONTROL [patent_app_type] => utility [patent_app_number] => 17/546186 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546186
METHOD OF FORMING STRUCTURES FOR THRESHOLD VOLTAGE CONTROL Dec 8, 2021 Pending
Array ( [id] => 18494216 [patent_doc_number] => 11699637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Vertically stacked transistor devices with isolation wall structures containing an electrical conductor [patent_app_type] => utility [patent_app_number] => 17/547066 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9442 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547066
Vertically stacked transistor devices with isolation wall structures containing an electrical conductor Dec 8, 2021 Issued
Array ( [id] => 17486265 [patent_doc_number] => 20220093769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE [patent_app_type] => utility [patent_app_number] => 17/544652 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544652
Method for fabricating semiconductor device with programmable feature Dec 6, 2021 Issued
Array ( [id] => 17886459 [patent_doc_number] => 20220301937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => EDGE FIN TRIM PROCESS [patent_app_type] => utility [patent_app_number] => 17/521610 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521610
EDGE FIN TRIM PROCESS Nov 7, 2021 Pending
Array ( [id] => 17795558 [patent_doc_number] => 20220254650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/517304 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517304
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE Nov 1, 2021 Pending
Array ( [id] => 18345186 [patent_doc_number] => 20230133296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => INTEGRATING STANDARD-GATE TRANSISTORS AND EXTENDED-GATE TRANSISTORS ON THE SAME SUBSTRATE USING LOW-TEMPERATURE GATE DIELECTRIC TREATMENTS [patent_app_type] => utility [patent_app_number] => 17/512784 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512784
INTEGRATING STANDARD-GATE TRANSISTORS AND EXTENDED-GATE TRANSISTORS ON THE SAME SUBSTRATE USING LOW-TEMPERATURE GATE DIELECTRIC TREATMENTS Oct 27, 2021 Pending
Array ( [id] => 19168534 [patent_doc_number] => 11984448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/509265 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 13875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509265
Semiconductor device Oct 24, 2021 Issued
Array ( [id] => 17963962 [patent_doc_number] => 20220344543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MICRO LIGHT-EMITTING DIODE STRUCTURE AND MICRO LIGHT-EMITTING DIODE DISPLAY PANEL USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/501310 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501310
Micro light-emitting diode structure and micro light-emitting diode display panel using the same Oct 13, 2021 Issued
Array ( [id] => 17630745 [patent_doc_number] => 20220165760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => IMAGE SENSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/499698 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499698
IMAGE SENSING DEVICE Oct 11, 2021 Pending
Array ( [id] => 17551762 [patent_doc_number] => 20220123104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => CAPACITOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/450520 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450520
CAPACITOR STRUCTURE AND FORMING METHOD THEREOF Oct 10, 2021 Pending
Array ( [id] => 18286693 [patent_doc_number] => 20230102165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => CONTACT STRUCTURE FORMATION FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/484453 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484453
CONTACT STRUCTURE FORMATION FOR MEMORY DEVICES Sep 23, 2021 Pending
Array ( [id] => 17709172 [patent_doc_number] => 20220209180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/481111 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481111
Display device Sep 20, 2021 Issued
Array ( [id] => 18112976 [patent_doc_number] => 20230005856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/480852 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 90819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480852
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME Sep 20, 2021 Pending
Array ( [id] => 18639567 [patent_doc_number] => 11764190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => 3D stacked compute and memory with copper pillars [patent_app_type] => utility [patent_app_number] => 17/472325 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10390 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472325
3D stacked compute and memory with copper pillars Sep 9, 2021 Issued
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