Search

Viren A. Thakur

Examiner (ID: 7657, Phone: (571)272-6694 , Office: P/1792 )

Most Active Art Unit
1792
Art Unit(s)
1794, 1792, 1782, 1761
Total Applications
1003
Issued Applications
117
Pending Applications
125
Abandoned Applications
778

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18848959 [patent_doc_number] => 20230411363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MULTI-LAYER STACKED CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 18/210091 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 572 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/210091
Multi-layer stacked chip package Jun 14, 2023 Issued
Array ( [id] => 19436037 [patent_doc_number] => 20240304535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Integrated Circuit Package and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/334695 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334695 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334695
Integrated Circuit Package and Methods of Forming the Same Jun 13, 2023 Pending
Array ( [id] => 19148621 [patent_doc_number] => 20240147739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/208979 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208979
SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME Jun 12, 2023 Pending
Array ( [id] => 18661408 [patent_doc_number] => 20230307422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/325769 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325769
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME May 29, 2023 Pending
Array ( [id] => 18653932 [patent_doc_number] => 20230299774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/202915 [patent_app_country] => US [patent_app_date] => 2023-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 56541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202915
LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS May 26, 2023 Pending
Array ( [id] => 18812695 [patent_doc_number] => 20230387032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/202310 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202310
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF May 25, 2023 Pending
Array ( [id] => 19604767 [patent_doc_number] => 20240395647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Semiconductor Device and Method of Forming Channels in Encapsulant to Reduce Warpage in Reconstituted Wafer [patent_app_type] => utility [patent_app_number] => 18/323594 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323594
Semiconductor Device and Method of Forming Channels in Encapsulant to Reduce Warpage in Reconstituted Wafer May 24, 2023 Pending
Array ( [id] => 18661453 [patent_doc_number] => 20230307467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/200052 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200052
SEMICONDUCTOR DEVICE May 21, 2023 Abandoned
Array ( [id] => 18615794 [patent_doc_number] => 20230282533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/315558 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315558
Interposer and semiconductor package including the same May 10, 2023 Issued
Array ( [id] => 19575187 [patent_doc_number] => 20240379479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Semiconductor Device and Method of Making a Fan-Out Semiconductor Package with Pre-Assembled Passive Modules [patent_app_type] => utility [patent_app_number] => 18/315098 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315098
Semiconductor Device and Method of Making a Fan-Out Semiconductor Package with Pre-Assembled Passive Modules May 9, 2023 Pending
Array ( [id] => 18601907 [patent_doc_number] => 20230276713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => TECHNIQUES FOR MRAM MTJ TOP ELECTRODE CONNECTION [patent_app_type] => utility [patent_app_number] => 18/313469 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313469
Techniques for MRAM MTJ top electrode connection May 7, 2023 Issued
Array ( [id] => 18712893 [patent_doc_number] => 20230335526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => HIGH-DENSITY-INTERCONNECTION PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME [patent_app_type] => utility [patent_app_number] => 18/132602 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132602 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132602
HIGH-DENSITY-INTERCONNECTION PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME Apr 9, 2023 Pending
Array ( [id] => 18500586 [patent_doc_number] => 20230223381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/179013 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179013
Semiconductor integrated circuit device and semiconductor package structure Mar 5, 2023 Issued
Array ( [id] => 18456570 [patent_doc_number] => 20230197852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => Source/Drain Structure [patent_app_type] => utility [patent_app_number] => 18/174045 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174045
Source/drain structure Feb 23, 2023 Issued
Array ( [id] => 19321628 [patent_doc_number] => 20240243175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS [patent_app_type] => utility [patent_app_number] => 18/098188 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098188
TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS Jan 17, 2023 Pending
Array ( [id] => 19007881 [patent_doc_number] => 20240071952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/152502 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152502
INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME Jan 9, 2023 Pending
Array ( [id] => 19054753 [patent_doc_number] => 20240096722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Fan-Out Stacked Package and Methods of Making the Same [patent_app_type] => utility [patent_app_number] => 18/152539 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152539
Fan-Out Stacked Package and Methods of Making the Same Jan 9, 2023 Pending
Array ( [id] => 18714793 [patent_doc_number] => 20230337438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/152310 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152310
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Jan 9, 2023 Pending
Array ( [id] => 18833902 [patent_doc_number] => 20230402429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => Methods of Forming Packages and Resulting Structures [patent_app_type] => utility [patent_app_number] => 18/151758 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151758
Methods of Forming Packages and Resulting Structures Jan 8, 2023 Pending
Array ( [id] => 19023193 [patent_doc_number] => 20240079364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Die Structures and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/151856 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151856
Die Structures and Methods of Forming the Same Jan 8, 2023 Pending
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