Search

Viren A. Thakur

Examiner (ID: 7657, Phone: (571)272-6694 , Office: P/1792 )

Most Active Art Unit
1792
Art Unit(s)
1794, 1792, 1782, 1761
Total Applications
1003
Issued Applications
117
Pending Applications
125
Abandoned Applications
778

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18222998 [patent_doc_number] => 20230061992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/488766 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488766
Three-dimensional memory device and methods for forming the same Sep 28, 2021 Issued
Array ( [id] => 18279690 [patent_doc_number] => 20230095162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Semiconductor Devices and Methods for Forming a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/448714 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448714
Semiconductor devices and methods for forming a semiconductor device Sep 23, 2021 Issued
Array ( [id] => 18267854 [patent_doc_number] => 20230089096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MULTIPLE DIES COUPLED WITH A GLASS CORE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/481234 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481234
MULTIPLE DIES COUPLED WITH A GLASS CORE SUBSTRATE Sep 20, 2021 Pending
Array ( [id] => 17708641 [patent_doc_number] => 20220208649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/479278 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479278
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Sep 19, 2021 Abandoned
Array ( [id] => 17339641 [patent_doc_number] => 20220005972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => IMAGE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/476740 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476740
Image display device Sep 15, 2021 Issued
Array ( [id] => 19229705 [patent_doc_number] => 12009349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Vertical semiconductor package including horizontally stacked dies and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/476703 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476703
Vertical semiconductor package including horizontally stacked dies and methods of forming the same Sep 15, 2021 Issued
Array ( [id] => 19399775 [patent_doc_number] => 12074163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor structure and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/447107 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7663 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447107
Semiconductor structure and fabrication method thereof Sep 7, 2021 Issued
Array ( [id] => 19597042 [patent_doc_number] => 12154896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Three-dimensional integrated circuit packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/460353 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 8717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460353 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460353
Three-dimensional integrated circuit packages and methods of forming the same Aug 29, 2021 Issued
Array ( [id] => 20111587 [patent_doc_number] => 12362323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Three-dimensional integrated circuit [patent_app_type] => utility [patent_app_number] => 17/460181 [patent_app_country] => US [patent_app_date] => 2021-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460181
Three-dimensional integrated circuit Aug 27, 2021 Issued
Array ( [id] => 18226730 [patent_doc_number] => 20230065724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH CONDUCTIVE BUMPS [patent_app_type] => utility [patent_app_number] => 17/459135 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459135
Structure and formation method of semiconductor device with conductive bumps Aug 26, 2021 Issued
Array ( [id] => 17692287 [patent_doc_number] => 20220199580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/412554 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412554
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Aug 25, 2021 Abandoned
Array ( [id] => 18213167 [patent_doc_number] => 20230059431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => STACKED DIE INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING INTERPOSER FOR COUPLING AN UPPER STACKED DIE(S) TO A PACKAGE SUBSTRATE FOR PACKAGE HEIGHT REDUCTION, AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/409481 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409481
STACKED DIE INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING INTERPOSER FOR COUPLING AN UPPER STACKED DIE(S) TO A PACKAGE SUBSTRATE FOR PACKAGE HEIGHT REDUCTION, AND RELATED FABRICATION METHODS Aug 22, 2021 Pending
Array ( [id] => 18669991 [patent_doc_number] => 11776903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Semiconductor apparatus and method of making the same [patent_app_type] => utility [patent_app_number] => 17/445227 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445227
Semiconductor apparatus and method of making the same Aug 16, 2021 Issued
Array ( [id] => 18661536 [patent_doc_number] => 20230307550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/020758 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18020758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/020758
SEMICONDUCTOR DEVICE Aug 16, 2021 Pending
Array ( [id] => 17247148 [patent_doc_number] => 20210366893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together [patent_app_type] => utility [patent_app_number] => 17/397176 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397176
Semiconductor Device that Uses Bonding Layer to Join Semiconductor Substrates Together Aug 8, 2021 Pending
Array ( [id] => 18181709 [patent_doc_number] => 20230042438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => BONDED ASSEMBLY INCLUDING INTER-DIE VIA STRUCTURES AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/396291 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396291
Bonded assembly including inter-die via structures and methods for making the same Aug 5, 2021 Issued
Array ( [id] => 17692236 [patent_doc_number] => 20220199529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/392936 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392936
Semiconductor package Aug 2, 2021 Issued
Array ( [id] => 19260935 [patent_doc_number] => 12021000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor package and method for fabricating a semiconductor package [patent_app_type] => utility [patent_app_number] => 17/386654 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5124 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386654
Semiconductor package and method for fabricating a semiconductor package Jul 27, 2021 Issued
Array ( [id] => 17855275 [patent_doc_number] => 20220285318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/382916 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382916 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382916
Semiconductor packages and methods for forming the same Jul 21, 2021 Issued
Array ( [id] => 19016341 [patent_doc_number] => 11923283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Semiconductor package and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/382872 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9113 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382872
Semiconductor package and method for fabricating the same Jul 21, 2021 Issued
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