Search

Vit W. Miska

Examiner (ID: 5149, Phone: (571)272-2108 , Office: P/2833 )

Most Active Art Unit
2107
Art Unit(s)
2833, 2103, 2203, 2107, 2859, 3105, 2112, 2856, 2841, 2899
Total Applications
3372
Issued Applications
2863
Pending Applications
96
Abandoned Applications
416

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11411808 [patent_doc_number] => 09559124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Display panel' [patent_app_type] => utility [patent_app_number] => 14/340412 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11756 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340412
Display panel Jul 23, 2014 Issued
Array ( [id] => 11681276 [patent_doc_number] => 09679812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Semiconductor device with self-aligned contact' [patent_app_type] => utility [patent_app_number] => 14/340413 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340413 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340413
Semiconductor device with self-aligned contact Jul 23, 2014 Issued
Array ( [id] => 10394820 [patent_doc_number] => 20150279827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'OPTICAL MODULE INTEGRATED PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/337721 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337721
Optical module integrated package Jul 21, 2014 Issued
Array ( [id] => 10385278 [patent_doc_number] => 20150270286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 14/337476 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337476
Array substrate and method for manufacturing the same, display panel Jul 21, 2014 Issued
Array ( [id] => 10674049 [patent_doc_number] => 20160020193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A CAPACITOR IN A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/334521 [patent_app_country] => US [patent_app_date] => 2014-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14334521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/334521
Package on package (PoP) integrated device comprising a capacitor in a substrate Jul 16, 2014 Issued
Array ( [id] => 11809606 [patent_doc_number] => 09714166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Thin film structure for hermetic sealing' [patent_app_type] => utility [patent_app_number] => 14/332461 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4425 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/332461
Thin film structure for hermetic sealing Jul 15, 2014 Issued
Array ( [id] => 10924102 [patent_doc_number] => 20140327123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD' [patent_app_type] => utility [patent_app_number] => 14/331670 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3219 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331670 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331670
PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD Jul 14, 2014 Abandoned
Array ( [id] => 10172268 [patent_doc_number] => 09202981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'LED array' [patent_app_type] => utility [patent_app_number] => 14/330914 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 2809 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330914 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330914
LED array Jul 13, 2014 Issued
Array ( [id] => 11207845 [patent_doc_number] => 09437476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method of manufacturing semiconductor device including air gap between patterns' [patent_app_type] => utility [patent_app_number] => 14/325789 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 78 [patent_no_of_words] => 6791 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325789
Method of manufacturing semiconductor device including air gap between patterns Jul 7, 2014 Issued
Array ( [id] => 11660125 [patent_doc_number] => 09673137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Electronic device having a lead with selectively modified electrical properties' [patent_app_type] => utility [patent_app_number] => 14/902158 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/902158
Electronic device having a lead with selectively modified electrical properties Jul 1, 2014 Issued
Array ( [id] => 10912337 [patent_doc_number] => 20140315353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'FABRICATION METHOD OF PACKAGING SUBSTRATE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/322372 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322372 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322372
Fabrication method of packaging substrate, and fabrication method of semiconductor package Jul 1, 2014 Issued
Array ( [id] => 10659572 [patent_doc_number] => 20160005716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'Semiconductor Package and Method' [patent_app_type] => utility [patent_app_number] => 14/321365 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8330 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321365
Semiconductor package for thermal dissipation Jun 30, 2014 Issued
Array ( [id] => 10659484 [patent_doc_number] => 20160005628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'WAFER LEVEL PACKAGING METHOD AND INTEGRATED ELECTRONIC PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/321261 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7423 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321261 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321261
Wafer level packaging method Jun 30, 2014 Issued
Array ( [id] => 10195833 [patent_doc_number] => 09224747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Vertical NAND device with shared word line steps' [patent_app_type] => utility [patent_app_number] => 14/320865 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 85 [patent_no_of_words] => 13566 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320865 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320865
Vertical NAND device with shared word line steps Jun 30, 2014 Issued
Array ( [id] => 9789791 [patent_doc_number] => 20150001735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'MULTIPATTERNING VIA SHRINK METHOD USING ALD SPACER' [patent_app_type] => utility [patent_app_number] => 14/320326 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320326
MULTIPATTERNING VIA SHRINK METHOD USING ALD SPACER Jun 29, 2014 Abandoned
Array ( [id] => 9790815 [patent_doc_number] => 20150002759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'TOUCH SENSOR BUILT-IN DISPLAY DEVICE AND TERMINAL CONNECTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/314362 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5050 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314362 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314362
Touch sensor built-in display device and terminal connection structure Jun 24, 2014 Issued
Array ( [id] => 10495334 [patent_doc_number] => 20150380357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/314779 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314779 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314779
Semiconductor device Jun 24, 2014 Issued
Array ( [id] => 11781821 [patent_doc_number] => 09391020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Interconnect structure having large self-aligned vias' [patent_app_type] => utility [patent_app_number] => 14/314945 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 7407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314945 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314945
Interconnect structure having large self-aligned vias Jun 24, 2014 Issued
Array ( [id] => 10609421 [patent_doc_number] => 09329449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Display panel, display apparatus and method for manufacturing display panel' [patent_app_type] => utility [patent_app_number] => 14/313581 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5025 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313581 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/313581
Display panel, display apparatus and method for manufacturing display panel Jun 23, 2014 Issued
Array ( [id] => 10638629 [patent_doc_number] => 09356142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Pattern layout to prevent split gate flash memory cell failure' [patent_app_type] => utility [patent_app_number] => 14/310277 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 8934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310277 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310277
Pattern layout to prevent split gate flash memory cell failure Jun 19, 2014 Issued
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