Search

Vit W. Miska

Examiner (ID: 5149, Phone: (571)272-2108 , Office: P/2833 )

Most Active Art Unit
2107
Art Unit(s)
2833, 2103, 2203, 2107, 2859, 3105, 2112, 2856, 2841, 2899
Total Applications
3372
Issued Applications
2863
Pending Applications
96
Abandoned Applications
416

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8858465 [patent_doc_number] => 08461000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Method of making ultrahigh density vertical NAND memory device' [patent_app_type] => utility [patent_app_number] => 13/693337 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 85 [patent_no_of_words] => 17584 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693337 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693337
Method of making ultrahigh density vertical NAND memory device Dec 3, 2012 Issued
Array ( [id] => 8767550 [patent_doc_number] => 20130095587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'METHODS FOR MANUFACTURING THIN FILM TRANSISTOR AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/692310 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 30446 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692310
Methods for manufacturing thin film transistor and display device Dec 2, 2012 Issued
Array ( [id] => 8995648 [patent_doc_number] => 08519536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process' [patent_app_type] => utility [patent_app_number] => 13/691427 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691427
Semiconductor device including bump formed on substrate to prevent extremely-low dielectric constant (ELK) interlayer dielectric layer (ILD) delamination during reflow process Nov 29, 2012 Issued
Array ( [id] => 8731730 [patent_doc_number] => 20130077299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'HIGH VOLTAGE ARRAY LIGHT EMITTING DIODE (LED) DEVICES, FIXTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/671089 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 26413 [patent_no_of_claims] => 118 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671089 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671089
High voltage array light emitting diode (LED) devices and fixtures Nov 6, 2012 Issued
Array ( [id] => 8995515 [patent_doc_number] => 08519400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Light pipe etch control for CMOS fabrication' [patent_app_type] => utility [patent_app_number] => 13/662562 [patent_app_country] => US [patent_app_date] => 2012-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4811 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662562
Light pipe etch control for CMOS fabrication Oct 28, 2012 Issued
Array ( [id] => 8668942 [patent_doc_number] => 20130043480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'Exposure Device, Exposure Method and Method of Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/659205 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17389 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659205
Display device Oct 23, 2012 Issued
Array ( [id] => 9575098 [patent_doc_number] => 08765510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Semiconductor diodes fabricated by aspect ratio trapping with coalesced films' [patent_app_type] => utility [patent_app_number] => 13/650206 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 11059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/650206
Semiconductor diodes fabricated by aspect ratio trapping with coalesced films Oct 11, 2012 Issued
Array ( [id] => 9316427 [patent_doc_number] => 20140048765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/812500 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4133 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13812500 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/812500
Method for manufacturing semiconductor device Oct 11, 2012 Issued
Array ( [id] => 8982542 [patent_doc_number] => 08513660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Organic optoelectronic device and making method thereof' [patent_app_type] => utility [patent_app_number] => 13/647232 [patent_app_country] => US [patent_app_date] => 2012-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13647232 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/647232
Organic optoelectronic device and making method thereof Oct 7, 2012 Issued
Array ( [id] => 9406276 [patent_doc_number] => 20140097528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'CHIP ARRANGEMENTS, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 13/645548 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4943 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645548 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645548
Chip arrangements, a chip package and a method for manufacturing a chip arrangement Oct 4, 2012 Issued
Array ( [id] => 9406231 [patent_doc_number] => 20140097483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => '3-D SINGLE FLOATING GATE NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/644880 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2994 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644880 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644880
3-D single floating gate non-volatile memory device Oct 3, 2012 Issued
Array ( [id] => 9406182 [patent_doc_number] => 20140097434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS' [patent_app_type] => utility [patent_app_number] => 13/644918 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6362 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644918 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644918
Back-end-of-line metal-oxide-semiconductor varactors Oct 3, 2012 Issued
Array ( [id] => 9406274 [patent_doc_number] => 20140097526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'PACKAGED IC HAVING PRINTED DIELECTRIC ADHESIVE ON DIE PAD' [patent_app_type] => utility [patent_app_number] => 13/644627 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644627
Packaged IC having printed dielectric adhesive on die pad Oct 3, 2012 Issued
Array ( [id] => 9711437 [patent_doc_number] => 08836012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Spacer design to prevent trapped electrons' [patent_app_type] => utility [patent_app_number] => 13/644901 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3919 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644901 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644901
Spacer design to prevent trapped electrons Oct 3, 2012 Issued
Array ( [id] => 9413460 [patent_doc_number] => 08697496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-15 [patent_title] => 'Method of manufacture integrated circuit package' [patent_app_type] => utility [patent_app_number] => 13/644647 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3172 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644647
Method of manufacture integrated circuit package Oct 3, 2012 Issued
Array ( [id] => 9389952 [patent_doc_number] => 08686556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Wafer level applied thermal heat sink' [patent_app_type] => utility [patent_app_number] => 13/644579 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2017 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644579 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644579
Wafer level applied thermal heat sink Oct 3, 2012 Issued
Array ( [id] => 9523963 [patent_doc_number] => 08748226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Method for fixing semiconductor chip on circuit board' [patent_app_type] => utility [patent_app_number] => 13/645482 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2785 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645482
Method for fixing semiconductor chip on circuit board Oct 3, 2012 Issued
Array ( [id] => 8742518 [patent_doc_number] => 20130082235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'MONOLITHIC 3-D INTEGRATION USING GRAPHENE' [patent_app_type] => utility [patent_app_number] => 13/644720 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644720
Semiconductor device and methods of making semiconductor device using graphene Oct 3, 2012 Issued
Array ( [id] => 9376399 [patent_doc_number] => 08680664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Structure for encapsulating an electronic device' [patent_app_type] => utility [patent_app_number] => 13/644444 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5388 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644444 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/644444
Structure for encapsulating an electronic device Oct 3, 2012 Issued
Array ( [id] => 8753535 [patent_doc_number] => 20130087839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'DYNAMIC MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/645476 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3921 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645476
Dynamic memory structure Oct 3, 2012 Issued
Menu