Search

Vu A. Vu

Examiner (ID: 11603)

Most Active Art Unit
2828
Art Unit(s)
2823, 2897, 2828
Total Applications
1405
Issued Applications
1214
Pending Applications
128
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 947667 [patent_doc_number] => 06965982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread' [patent_app_type] => utility [patent_app_number] => 09/895227 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5586 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965982.pdf [firstpage_image] =>[orig_patent_app_number] => 09895227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895227
Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread Jun 28, 2001 Issued
09/895582 Dynamically controlling execution of operations within a multi-operation instruction Jun 28, 2001 Abandoned
Array ( [id] => 771388 [patent_doc_number] => 07010670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer' [patent_app_type] => utility [patent_app_number] => 09/894205 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 24152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010670.pdf [firstpage_image] =>[orig_patent_app_number] => 09894205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894205
Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer Jun 27, 2001 Issued
Array ( [id] => 6881020 [patent_doc_number] => 20010032308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Method and apparatus for performing predicate prediction' [patent_app_type] => new [patent_app_number] => 09/884718 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032308.pdf [firstpage_image] =>[orig_patent_app_number] => 09884718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884718
Method and apparatus for performing predicate prediction Jun 17, 2001 Issued
Array ( [id] => 7615397 [patent_doc_number] => 06948050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware' [patent_app_type] => utility [patent_app_number] => 09/875136 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 64 [patent_no_of_words] => 38162 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948050.pdf [firstpage_image] =>[orig_patent_app_number] => 09875136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875136
Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware Jun 5, 2001 Issued
Array ( [id] => 1501606 [patent_doc_number] => 06405306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Instruction set for bi-directional conversion and transfer of integer and floating point data' [patent_app_type] => B2 [patent_app_number] => 09/866078 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4389 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405306.pdf [firstpage_image] =>[orig_patent_app_number] => 09866078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866078
Instruction set for bi-directional conversion and transfer of integer and floating point data May 24, 2001 Issued
Array ( [id] => 7001784 [patent_doc_number] => 20010054138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Instruction buffer and buffer queue control method' [patent_app_type] => new [patent_app_number] => 09/862471 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054138.pdf [firstpage_image] =>[orig_patent_app_number] => 09862471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862471
Instruction buffer and method of controlling the instruction buffer where buffer entries are issued in a predetermined order May 22, 2001 Issued
Array ( [id] => 6554905 [patent_doc_number] => 20020194462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line' [patent_app_type] => new [patent_app_number] => 09/849754 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 22806 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194462.pdf [firstpage_image] =>[orig_patent_app_number] => 09849754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849754
Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line May 3, 2001 Abandoned
Array ( [id] => 6579757 [patent_doc_number] => 20020166008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Data processing system and multiprocessor system' [patent_app_type] => new [patent_app_number] => 09/838012 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9132 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20020166008.pdf [firstpage_image] =>[orig_patent_app_number] => 09838012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838012
Data processing system and multiprocessor system Apr 18, 2001 Issued
Array ( [id] => 5910554 [patent_doc_number] => 20020144090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Apparatus, method and system for fast register renaming using virtual renaming' [patent_app_type] => new [patent_app_number] => 09/822938 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6362 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144090.pdf [firstpage_image] =>[orig_patent_app_number] => 09822938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/822938
Apparatus, method and system for fast register renaming using virtual renaming, including by using rename information or a renamed register Mar 29, 2001 Issued
Array ( [id] => 5910565 [patent_doc_number] => 20020144101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Caching DAG traces' [patent_app_type] => new [patent_app_number] => 09/823235 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5970 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144101.pdf [firstpage_image] =>[orig_patent_app_number] => 09823235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823235
Caching DAG traces Mar 29, 2001 Abandoned
Array ( [id] => 731235 [patent_doc_number] => 07047392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Data processing apparatus and method for controlling staged multi-pipeline processing' [patent_app_type] => utility [patent_app_number] => 09/818910 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 4100 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047392.pdf [firstpage_image] =>[orig_patent_app_number] => 09818910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818910
Data processing apparatus and method for controlling staged multi-pipeline processing Mar 27, 2001 Issued
Array ( [id] => 6561375 [patent_doc_number] => 20020138714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution' [patent_app_type] => new [patent_app_number] => 09/816291 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5148 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138714.pdf [firstpage_image] =>[orig_patent_app_number] => 09816291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816291
Scoreboard for scheduling of instructions in a microprocessor that provides out of order execution Mar 21, 2001 Abandoned
Array ( [id] => 5971464 [patent_doc_number] => 20020091909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Matrix processing method of shared-memory scalar parallel-processing computer and recording medium' [patent_app_type] => new [patent_app_number] => 09/811484 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091909.pdf [firstpage_image] =>[orig_patent_app_number] => 09811484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811484
Matrix processing method of shared-memory scalar parallel-processing computer and recording medium Mar 19, 2001 Issued
Array ( [id] => 6988708 [patent_doc_number] => 20010037441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (CLIW)' [patent_app_type] => new [patent_app_number] => 09/809053 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037441.pdf [firstpage_image] =>[orig_patent_app_number] => 09809053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809053
Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (CLIW) Mar 15, 2001 Issued
Array ( [id] => 6922160 [patent_doc_number] => 20010029576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Data driven information processor carrying out processing using packet stored with plurality of operand data' [patent_app_type] => new [patent_app_number] => 09/805164 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10717 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029576.pdf [firstpage_image] =>[orig_patent_app_number] => 09805164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805164
Data driven information processor carrying out processing using packet stored with plurality of operand data Mar 13, 2001 Issued
Array ( [id] => 1161662 [patent_doc_number] => 06775763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Bytecode instruction processor with switch instruction handling logic' [patent_app_type] => B2 [patent_app_number] => 09/802594 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8319 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775763.pdf [firstpage_image] =>[orig_patent_app_number] => 09802594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802594
Bytecode instruction processor with switch instruction handling logic Mar 8, 2001 Issued
Array ( [id] => 6001652 [patent_doc_number] => 20020029332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Processing architecture having an array bounds check capability' [patent_app_type] => new [patent_app_number] => 09/802196 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5348 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029332.pdf [firstpage_image] =>[orig_patent_app_number] => 09802196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802196
Processing architecture having an array bounds check capability Mar 7, 2001 Issued
Array ( [id] => 5876888 [patent_doc_number] => 20020049892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Computer processing architecture having a scalable number of processing paths and pipelines' [patent_app_type] => new [patent_app_number] => 09/802108 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9158 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20020049892.pdf [firstpage_image] =>[orig_patent_app_number] => 09802108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802108
Computer processing architecture having a scalable number of processing paths and pipelines Mar 7, 2001 Issued
Array ( [id] => 7623813 [patent_doc_number] => 06725364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Configurable processor system' [patent_app_type] => B1 [patent_app_number] => 09/803524 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1852 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725364.pdf [firstpage_image] =>[orig_patent_app_number] => 09803524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803524
Configurable processor system Mar 7, 2001 Issued
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