Vu A. Vu

Array ( [id] => 965687 [patent_doc_number] => 06950926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Use of a neutral instruction as a dependency indicator for a set of instructions' [patent_app_type] => utility [patent_app_number] => 09/798177 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3381 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950926.pdf [firstpage_image] =>[orig_patent_app_number] => 09798177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1084964 [patent_doc_number] => 06834295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller' [patent_app_type] => B2 [patent_app_number] => 09/791940 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6278 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834295.pdf [firstpage_image] =>[orig_patent_app_number] => 09791940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7601947 [patent_doc_number] => 07237097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Partial bitwise permutations' [patent_app_type] => utility [patent_app_number] => 09/788683 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 7562 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237097.pdf [firstpage_image] =>[orig_patent_app_number] => 09788683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 984645 [patent_doc_number] => 06928532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Logic integrated circuit, and recording medium readable by a computer, which stores a source of CPU core on said logic integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/772027 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6058 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928532.pdf [firstpage_image] =>[orig_patent_app_number] => 09772027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5990709 [patent_doc_number] => 20020099927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'System and method for determining operand access to data' [patent_app_type] => new [patent_app_number] => 09/766685 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3584 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099927.pdf [firstpage_image] =>[orig_patent_app_number] => 09766685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6099112 [patent_doc_number] => 20020053016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Solving parallel problems employing hardware multi-threading in a parallel processing environment' [patent_app_type] => new [patent_app_number] => 09/759380 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053016.pdf [firstpage_image] =>[orig_patent_app_number] => 09759380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1030620 [patent_doc_number] => 06883089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method and apparatus for processing a predicated instruction using limited predicate slip' [patent_app_type] => utility [patent_app_number] => 09/751861 [patent_app_country] => US [patent_app_date] => 2000-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 3916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883089.pdf [firstpage_image] =>[orig_patent_app_number] => 09751861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7601954 [patent_doc_number] => 07237090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'Configurable out-of-order data transfer in a coprocessor interface' [patent_app_type] => utility [patent_app_number] => 09/751747 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12463 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237090.pdf [firstpage_image] =>[orig_patent_app_number] => 09751747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 411422 [patent_doc_number] => 07287147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Configurable co-processor interface' [patent_app_type] => utility [patent_app_number] => 09/751748 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287147.pdf [firstpage_image] =>[orig_patent_app_number] => 09751748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6648689 [patent_doc_number] => 20020087835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method and apparatus for improving dispersal performance in a processor through the use of no-op ports' [patent_app_type] => new [patent_app_number] => 09/753060 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087835.pdf [firstpage_image] =>[orig_patent_app_number] => 09753060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6648833 [patent_doc_number] => 20020087853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Security on hardware loops' [patent_app_type] => new [patent_app_number] => 09/753081 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2621 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087853.pdf [firstpage_image] =>[orig_patent_app_number] => 09753081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6648646 [patent_doc_number] => 20020087831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Instruction packetization based on rename capacity' [patent_app_type] => new [patent_app_number] => 09/752573 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2861 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087831.pdf [firstpage_image] =>[orig_patent_app_number] => 09752573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7615393 [patent_doc_number] => 06948054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Simple branch prediction and misprediction recovery method' [patent_app_type] => utility [patent_app_number] => 09/726144 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2411 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948054.pdf [firstpage_image] =>[orig_patent_app_number] => 09726144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509054 [patent_doc_number] => 06467036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor' [patent_app_type] => B1 [patent_app_number] => 09/717992 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6912 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467036.pdf [firstpage_image] =>[orig_patent_app_number] => 09717992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557680 [patent_doc_number] => 06401212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden' [patent_app_type] => B1 [patent_app_number] => 09/708299 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401212.pdf [firstpage_image] =>[orig_patent_app_number] => 09708299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149701 [patent_doc_number] => 06782470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Operand queues for streaming data: A processor register file extension' [patent_app_type] => B1 [patent_app_number] => 09/706899 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2319 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782470.pdf [firstpage_image] =>[orig_patent_app_number] => 09706899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1250348 [patent_doc_number] => 06675372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Counting speculative and non-speculative events' [patent_app_type] => B1 [patent_app_number] => 09/703398 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2633 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675372.pdf [firstpage_image] =>[orig_patent_app_number] => 09703398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1438698 [patent_doc_number] => 06356993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Dual aspect ratio PE array with no connection switching' [patent_app_type] => B1 [patent_app_number] => 09/695895 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356993.pdf [firstpage_image] =>[orig_patent_app_number] => 09695895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1201024 [patent_doc_number] => 06728863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Wide connections for transferring data between PE\'s of an N-dimensional mesh-connected SIMD array while transferring operands from memory' [patent_app_type] => B1 [patent_app_number] => 09/696439 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5462 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728863.pdf [firstpage_image] =>[orig_patent_app_number] => 09696439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185892 [patent_doc_number] => 06745316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Data processing system' [patent_app_type] => B1 [patent_app_number] => 09/688440 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8658 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745316.pdf [firstpage_image] =>[orig_patent_app_number] => 09688440 [rel_patent_id] =>[rel_patent_doc_number] =>)