Search

Vu A. Vu

Examiner (ID: 11603)

Most Active Art Unit
2828
Art Unit(s)
2823, 2897, 2828
Total Applications
1405
Issued Applications
1214
Pending Applications
128
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1181202 [patent_doc_number] => 06754812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Hardware predication for conditional instruction path branching' [patent_app_type] => B1 [patent_app_number] => 09/610895 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754812.pdf [firstpage_image] =>[orig_patent_app_number] => 09610895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610895
Hardware predication for conditional instruction path branching Jul 5, 2000 Issued
Array ( [id] => 1298198 [patent_doc_number] => 06631465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for instruction re-alignment using a branch on a falsehood of a qualifying predicate' [patent_app_type] => B1 [patent_app_number] => 09/607684 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631465.pdf [firstpage_image] =>[orig_patent_app_number] => 09607684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607684
Method and apparatus for instruction re-alignment using a branch on a falsehood of a qualifying predicate Jun 29, 2000 Issued
Array ( [id] => 1124960 [patent_doc_number] => 06799268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Branch ordering buffer' [patent_app_type] => B1 [patent_app_number] => 09/607640 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3594 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799268.pdf [firstpage_image] =>[orig_patent_app_number] => 09607640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607640
Branch ordering buffer Jun 29, 2000 Issued
Array ( [id] => 1592413 [patent_doc_number] => 06360318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Configurable branch prediction for a processor performing speculative execution' [patent_app_type] => B1 [patent_app_number] => 09/608451 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9159 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360318.pdf [firstpage_image] =>[orig_patent_app_number] => 09608451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608451
Configurable branch prediction for a processor performing speculative execution Jun 28, 2000 Issued
Array ( [id] => 4299004 [patent_doc_number] => 06282639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Configurable branch prediction for a processor performing speculative execution' [patent_app_type] => 1 [patent_app_number] => 9/608448 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9015 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282639.pdf [firstpage_image] =>[orig_patent_app_number] => 608448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608448
Configurable branch prediction for a processor performing speculative execution Jun 28, 2000 Issued
Array ( [id] => 1325376 [patent_doc_number] => 06615343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution' [patent_app_type] => B1 [patent_app_number] => 09/599227 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2620 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615343.pdf [firstpage_image] =>[orig_patent_app_number] => 09599227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599227
Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution Jun 21, 2000 Issued
Array ( [id] => 1314542 [patent_doc_number] => 06622234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions' [patent_app_type] => B1 [patent_app_number] => 09/598564 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7220 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622234.pdf [firstpage_image] =>[orig_patent_app_number] => 09598564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598564
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions Jun 20, 2000 Issued
Array ( [id] => 1294972 [patent_doc_number] => 06640297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Link pipe system for storage and retrieval of sequences of branch addresses' [patent_app_type] => B1 [patent_app_number] => 09/596280 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8000 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640297.pdf [firstpage_image] =>[orig_patent_app_number] => 09596280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596280
Link pipe system for storage and retrieval of sequences of branch addresses Jun 18, 2000 Issued
Array ( [id] => 1524940 [patent_doc_number] => 06415376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Apparatus and method for issue grouping of instructions in a VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/595791 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9391 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415376.pdf [firstpage_image] =>[orig_patent_app_number] => 09595791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595791
Apparatus and method for issue grouping of instructions in a VLIW processor Jun 15, 2000 Issued
Array ( [id] => 1225714 [patent_doc_number] => 06704862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method and apparatus for facilitating exception handling using a conditional trap instruction' [patent_app_type] => B1 [patent_app_number] => 09/591142 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5475 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704862.pdf [firstpage_image] =>[orig_patent_app_number] => 09591142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591142
Method and apparatus for facilitating exception handling using a conditional trap instruction Jun 8, 2000 Issued
09/590552 HYBRID BULK/SOI MULTIPROCESSORS Jun 8, 2000 Abandoned
Array ( [id] => 1289257 [patent_doc_number] => 06647489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Compare branch instruction pairing within a single integer pipeline' [patent_app_type] => B1 [patent_app_number] => 09/590055 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 9710 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647489.pdf [firstpage_image] =>[orig_patent_app_number] => 09590055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590055
Compare branch instruction pairing within a single integer pipeline Jun 7, 2000 Issued
Array ( [id] => 1297200 [patent_doc_number] => 06633973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Trace control circuit adapted for high-speed microcomputer operation' [patent_app_type] => B1 [patent_app_number] => 09/588604 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 100 [patent_no_of_words] => 7728 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633973.pdf [firstpage_image] =>[orig_patent_app_number] => 09588604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588604
Trace control circuit adapted for high-speed microcomputer operation Jun 6, 2000 Issued
Array ( [id] => 1329230 [patent_doc_number] => 06606702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Multiprocessor speculation mechanism with imprecise recycling of storage operations' [patent_app_type] => B1 [patent_app_number] => 09/588606 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9529 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606702.pdf [firstpage_image] =>[orig_patent_app_number] => 09588606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588606
Multiprocessor speculation mechanism with imprecise recycling of storage operations Jun 5, 2000 Issued
Array ( [id] => 1326910 [patent_doc_number] => 06609192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'System and method for asynchronously overlapping storage barrier operations with old and new storage operations' [patent_app_type] => B1 [patent_app_number] => 09/588607 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9524 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609192.pdf [firstpage_image] =>[orig_patent_app_number] => 09588607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588607
System and method for asynchronously overlapping storage barrier operations with old and new storage operations Jun 5, 2000 Issued
Array ( [id] => 1310950 [patent_doc_number] => 06625660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Multiprocessor speculation mechanism for efficiently managing multiple barrier operations' [patent_app_type] => B1 [patent_app_number] => 09/588605 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9527 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625660.pdf [firstpage_image] =>[orig_patent_app_number] => 09588605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588605
Multiprocessor speculation mechanism for efficiently managing multiple barrier operations Jun 5, 2000 Issued
Array ( [id] => 1401342 [patent_doc_number] => 06564312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Data processor comprising an arithmetic logic unit' [patent_app_type] => B1 [patent_app_number] => 09/584812 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8876 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564312.pdf [firstpage_image] =>[orig_patent_app_number] => 09584812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584812
Data processor comprising an arithmetic logic unit May 30, 2000 Issued
Array ( [id] => 1348069 [patent_doc_number] => 06598146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Data-processing arrangement comprising a plurality of processing and memory circuits' [patent_app_type] => B1 [patent_app_number] => 09/580169 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8868 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598146.pdf [firstpage_image] =>[orig_patent_app_number] => 09580169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580169
Data-processing arrangement comprising a plurality of processing and memory circuits May 29, 2000 Issued
Array ( [id] => 1587497 [patent_doc_number] => 06425076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Instruction prediction based on filtering' [patent_app_type] => B1 [patent_app_number] => 09/544352 [patent_app_country] => US [patent_app_date] => 2000-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11023 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425076.pdf [firstpage_image] =>[orig_patent_app_number] => 09544352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/544352
Instruction prediction based on filtering Apr 5, 2000 Issued
Array ( [id] => 4349920 [patent_doc_number] => 06321322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Methods and apparatus for scalable instruction set architecture with dynamic compact instructions' [patent_app_type] => 1 [patent_app_number] => 9/543473 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321322.pdf [firstpage_image] =>[orig_patent_app_number] => 543473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543473
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions Apr 4, 2000 Issued
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