
Vu A. Vu
Examiner (ID: 13665)
| Most Active Art Unit | 2828 |
| Art Unit(s) | 2828, 2897, 2823 |
| Total Applications | 1445 |
| Issued Applications | 1233 |
| Pending Applications | 139 |
| Abandoned Applications | 98 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18359323
[patent_doc_number] => 20230140914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT BODY, AND SEMICONDUCTOR ELEMENT SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/915335
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7456
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17915335
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/915335 | Method for manufacturing semiconductor element, semiconductor element body, and semiconductor element substrate | Mar 28, 2021 | Issued |
Array
(
[id] => 18721451
[patent_doc_number] => 11798805
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Method for manufacturing semiconductor device and semiconductor substrate
[patent_app_type] => utility
[patent_app_number] => 17/211871
[patent_app_country] => US
[patent_app_date] => 2021-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 6898
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211871
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211871 | Method for manufacturing semiconductor device and semiconductor substrate | Mar 24, 2021 | Issued |
Array
(
[id] => 17326526
[patent_doc_number] => 11217551
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-01-04
[patent_title] => Chip package structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/209230
[patent_app_country] => US
[patent_app_date] => 2021-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 5255
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209230
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/209230 | Chip package structure and manufacturing method thereof | Mar 22, 2021 | Issued |
Array
(
[id] => 17373669
[patent_doc_number] => 20220028721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => METHOD FOR FABRICATING ELECTRONIC PACKAGE AND CARRIER STRUCTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/209494
[patent_app_country] => US
[patent_app_date] => 2021-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2290
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209494
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/209494 | Method for fabricating electronic package and carrier structure thereof | Mar 22, 2021 | Issued |
Array
(
[id] => 17780460
[patent_doc_number] => 20220246810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/209110
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209110
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/209110 | Package structure and manufacturing method thereof | Mar 21, 2021 | Issued |
Array
(
[id] => 17145260
[patent_doc_number] => 20210313273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE AND EMBEDDED PCB MODULE
[patent_app_type] => utility
[patent_app_number] => 17/208363
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208363
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/208363 | Method for fabricating a semiconductor package, semiconductor package and embedded PCB module | Mar 21, 2021 | Issued |
Array
(
[id] => 17115663
[patent_doc_number] => 20210296260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => SEMICONDUCTOR PACKAGING SUBSTRATE, FABRICATION METHOD AND PACKAGING PROCESS THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/202632
[patent_app_country] => US
[patent_app_date] => 2021-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202632
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202632 | Semiconductor packaging substrate, fabrication method and packaging process thereof | Mar 15, 2021 | Issued |
Array
(
[id] => 18277030
[patent_doc_number] => 11615978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Method for controlling flatness, method for forming coating film, apparatus for controlling flatness, and apparatus for forming coating film
[patent_app_type] => utility
[patent_app_number] => 17/198596
[patent_app_country] => US
[patent_app_date] => 2021-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 10741
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198596
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/198596 | Method for controlling flatness, method for forming coating film, apparatus for controlling flatness, and apparatus for forming coating film | Mar 10, 2021 | Issued |
Array
(
[id] => 16916704
[patent_doc_number] => 20210189796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => BUILDING MODEL GENERATION AND INTELLIGENT LIGHT CONTROL FOR SMART WINDOWS
[patent_app_type] => utility
[patent_app_number] => 17/195406
[patent_app_country] => US
[patent_app_date] => 2021-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10927
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195406
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/195406 | BUILDING MODEL GENERATION AND INTELLIGENT LIGHT CONTROL FOR SMART WINDOWS | Mar 7, 2021 | Abandoned |
Array
(
[id] => 18032070
[patent_doc_number] => 11515268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Semiconductor package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/192897
[patent_app_country] => US
[patent_app_date] => 2021-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 46
[patent_no_of_words] => 13248
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192897
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/192897 | Semiconductor package and manufacturing method thereof | Mar 4, 2021 | Issued |
Array
(
[id] => 17145181
[patent_doc_number] => 20210313194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/192964
[patent_app_country] => US
[patent_app_date] => 2021-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3365
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192964
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/192964 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS | Mar 4, 2021 | Abandoned |
Array
(
[id] => 17840703
[patent_doc_number] => 20220278009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => DMOS FET CHIP SCALE PACKAGE AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/187682
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2957
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187682
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187682 | DMOS FET chip scale package and method of making the same | Feb 25, 2021 | Issued |
Array
(
[id] => 18789288
[patent_doc_number] => 20230377938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => CHIP BONDING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/265902
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7395
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18265902
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/265902 | Chip bonding method | Feb 25, 2021 | Issued |
Array
(
[id] => 17716861
[patent_doc_number] => 11380862
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Light emitting diode display with redundancy scheme
[patent_app_type] => utility
[patent_app_number] => 17/186362
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 37
[patent_no_of_words] => 15577
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186362
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/186362 | Light emitting diode display with redundancy scheme | Feb 25, 2021 | Issued |
Array
(
[id] => 18321819
[patent_doc_number] => 20230119947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => A SUBSTRATE FOR MANUFACTURING DISPLAY DEVICE AND A MANUFACTURING METHOD USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/798219
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798219
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/798219 | Substrate for manufacturing display device and a manufacturing method using the same | Feb 25, 2021 | Issued |
Array
(
[id] => 18073661
[patent_doc_number] => 11532499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Semiconductor processing apparatus and method utilizing electrostatic discharge (ESD) prevention layer
[patent_app_type] => utility
[patent_app_number] => 17/182782
[patent_app_country] => US
[patent_app_date] => 2021-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 13983
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182782
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/182782 | Semiconductor processing apparatus and method utilizing electrostatic discharge (ESD) prevention layer | Feb 22, 2021 | Issued |
Array
(
[id] => 19765985
[patent_doc_number] => 12224287
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Display substrate and method for manufacturing the same, and display device
[patent_app_type] => utility
[patent_app_number] => 17/614662
[patent_app_country] => US
[patent_app_date] => 2021-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 7561
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17614662
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/614662 | Display substrate and method for manufacturing the same, and display device | Feb 18, 2021 | Issued |
Array
(
[id] => 18145432
[patent_doc_number] => 20230019288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => MOSFET WITH SATURATION CONTACT AND METHOD FOR FORMING A MOSFET WITH SATURATION CONTACT
[patent_app_type] => utility
[patent_app_number] => 17/783129
[patent_app_country] => US
[patent_app_date] => 2021-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17783129
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/783129 | MOSFET with saturation contact and method for forming a MOSFET with saturation contact | Feb 14, 2021 | Issued |
Array
(
[id] => 19951265
[patent_doc_number] => 12322636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Method for selecting semiconductor components
[patent_app_type] => utility
[patent_app_number] => 17/797671
[patent_app_country] => US
[patent_app_date] => 2021-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 1067
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17797671
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/797671 | Method for selecting semiconductor components | Feb 2, 2021 | Issued |
Array
(
[id] => 18175366
[patent_doc_number] => 11575085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Techniques for forming memory structures
[patent_app_type] => utility
[patent_app_number] => 17/165549
[patent_app_country] => US
[patent_app_date] => 2021-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 12058
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165549
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/165549 | Techniques for forming memory structures | Feb 1, 2021 | Issued |