Search

Vu A. Vu

Examiner (ID: 11603)

Most Active Art Unit
2828
Art Unit(s)
2823, 2897, 2828
Total Applications
1405
Issued Applications
1214
Pending Applications
128
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1326872 [patent_doc_number] => 06609188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Data flow processor' [patent_app_type] => B1 [patent_app_number] => 09/540196 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5878 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609188.pdf [firstpage_image] =>[orig_patent_app_number] => 09540196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540196
Data flow processor Mar 30, 2000 Issued
Array ( [id] => 1314534 [patent_doc_number] => 06622233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Hypercomputer' [patent_app_type] => B1 [patent_app_number] => 09/539318 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 15322 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622233.pdf [firstpage_image] =>[orig_patent_app_number] => 09539318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539318
Hypercomputer Mar 29, 2000 Issued
09/532787 Microprocessor Mar 21, 2000 Abandoned
Array ( [id] => 5803530 [patent_doc_number] => 20020010851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Emulated branch effected by trampoline mechanism' [patent_app_type] => new [patent_app_number] => 09/521160 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15276 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010851.pdf [firstpage_image] =>[orig_patent_app_number] => 09521160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521160
Emulated branch effected by trampoline mechanism Mar 7, 2000 Issued
Array ( [id] => 1423397 [patent_doc_number] => 06525748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method for downloading a sitemap from a server computer to a client computer in a web environment' [patent_app_type] => B1 [patent_app_number] => 09/516425 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525748.pdf [firstpage_image] =>[orig_patent_app_number] => 09516425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516425
Method for downloading a sitemap from a server computer to a client computer in a web environment Feb 29, 2000 Issued
Array ( [id] => 6689777 [patent_doc_number] => 20030033503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'SINGLE INSTRUCTION HAVING OPCODE AND STACK CONTROL FIELD' [patent_app_type] => new [patent_app_number] => 09/493960 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7980 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033503.pdf [firstpage_image] =>[orig_patent_app_number] => 09493960 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493960
Single instruction having op code and stack control field Jan 27, 2000 Issued
Array ( [id] => 1466336 [patent_doc_number] => 06393554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method and apparatus for performing vector and scalar multiplication and calculating rounded products' [patent_app_type] => B1 [patent_app_number] => 09/487771 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 15796 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393554.pdf [firstpage_image] =>[orig_patent_app_number] => 09487771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487771
Method and apparatus for performing vector and scalar multiplication and calculating rounded products Jan 18, 2000 Issued
Array ( [id] => 1415992 [patent_doc_number] => 06550003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Not reported jump buffer' [patent_app_type] => B1 [patent_app_number] => 09/479954 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4289 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550003.pdf [firstpage_image] =>[orig_patent_app_number] => 09479954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479954
Not reported jump buffer Jan 9, 2000 Issued
09/476622 External microcode Dec 30, 1999 Abandoned
Array ( [id] => 1348201 [patent_doc_number] => 06598156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Mechanism for handling failing load check instructions' [patent_app_type] => B1 [patent_app_number] => 09/471308 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5672 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598156.pdf [firstpage_image] =>[orig_patent_app_number] => 09471308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471308
Mechanism for handling failing load check instructions Dec 22, 1999 Issued
Array ( [id] => 749436 [patent_doc_number] => 07032100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Simple algorithmic cryptography engine' [patent_app_type] => utility [patent_app_number] => 09/466392 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6325 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032100.pdf [firstpage_image] =>[orig_patent_app_number] => 09466392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466392
Simple algorithmic cryptography engine Dec 16, 1999 Issued
Array ( [id] => 7626820 [patent_doc_number] => 06807624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Instruction control device and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/461429 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 69 [patent_no_of_words] => 15401 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807624.pdf [firstpage_image] =>[orig_patent_app_number] => 09461429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461429
Instruction control device and method therefor Dec 15, 1999 Issued
Array ( [id] => 1429387 [patent_doc_number] => 06530013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Instruction control apparatus for loading plurality of instructions into execution stage' [patent_app_type] => B1 [patent_app_number] => 09/461422 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3400 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530013.pdf [firstpage_image] =>[orig_patent_app_number] => 09461422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461422
Instruction control apparatus for loading plurality of instructions into execution stage Dec 15, 1999 Issued
Array ( [id] => 1386651 [patent_doc_number] => 06571363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Single event upset tolerant microprocessor architecture' [patent_app_type] => B1 [patent_app_number] => 09/464635 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4067 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571363.pdf [firstpage_image] =>[orig_patent_app_number] => 09464635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464635
Single event upset tolerant microprocessor architecture Dec 14, 1999 Issued
Array ( [id] => 1429087 [patent_doc_number] => 06513110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Check instruction and method' [patent_app_type] => B1 [patent_app_number] => 09/464644 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 8375 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513110.pdf [firstpage_image] =>[orig_patent_app_number] => 09464644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464644
Check instruction and method Dec 14, 1999 Issued
Array ( [id] => 1066749 [patent_doc_number] => 06851043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Branch instruction execution control apparatus' [patent_app_type] => utility [patent_app_number] => 09/461297 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 18928 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851043.pdf [firstpage_image] =>[orig_patent_app_number] => 09461297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461297
Branch instruction execution control apparatus Dec 14, 1999 Issued
Array ( [id] => 1139142 [patent_doc_number] => 06789185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Instruction control apparatus and method using micro program' [patent_app_type] => B1 [patent_app_number] => 09/460457 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6582 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789185.pdf [firstpage_image] =>[orig_patent_app_number] => 09460457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460457
Instruction control apparatus and method using micro program Dec 12, 1999 Issued
Array ( [id] => 1348165 [patent_doc_number] => 06598153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions' [patent_app_type] => B1 [patent_app_number] => 09/458407 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598153.pdf [firstpage_image] =>[orig_patent_app_number] => 09458407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458407
Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions Dec 9, 1999 Issued
Array ( [id] => 1337304 [patent_doc_number] => 06604193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Processor in which register number translation is carried out' [patent_app_type] => B1 [patent_app_number] => 09/458002 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604193.pdf [firstpage_image] =>[orig_patent_app_number] => 09458002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458002
Processor in which register number translation is carried out Dec 9, 1999 Issued
Array ( [id] => 1444135 [patent_doc_number] => 06496925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method and apparatus for processing an event occurrence within a multithreaded processor' [patent_app_type] => B1 [patent_app_number] => 09/458544 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 16367 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496925.pdf [firstpage_image] =>[orig_patent_app_number] => 09458544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458544
Method and apparatus for processing an event occurrence within a multithreaded processor Dec 8, 1999 Issued
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