Vu A. Vu

Array ( [id] => 1418980 [patent_doc_number] => 06546480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Instructions for arithmetic operations on vectored data' [patent_app_type] => B1 [patent_app_number] => 09/410998 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 15332 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546480.pdf [firstpage_image] =>[orig_patent_app_number] => 09410998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1584901 [patent_doc_number] => 06449712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions' [patent_app_type] => B1 [patent_app_number] => 09/410851 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7499 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449712.pdf [firstpage_image] =>[orig_patent_app_number] => 09410851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456807 [patent_doc_number] => 06457118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and system for selecting and using source operands in computer system instructions' [patent_app_type] => B1 [patent_app_number] => 09/410549 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3384 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457118.pdf [firstpage_image] =>[orig_patent_app_number] => 09410549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177712 [patent_doc_number] => 06760837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Bit field processor' [patent_app_type] => B1 [patent_app_number] => 09/410864 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 13360 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760837.pdf [firstpage_image] =>[orig_patent_app_number] => 09410864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568649 [patent_doc_number] => 06339812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method and apparatus for handling invalidation requests to processors not present in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/410139 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339812.pdf [firstpage_image] =>[orig_patent_app_number] => 09410139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395223 [patent_doc_number] => 06567883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and apparatus for command translation and enforcement of ordering of commands' [patent_app_type] => B1 [patent_app_number] => 09/384388 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7306 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567883.pdf [firstpage_image] =>[orig_patent_app_number] => 09384388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524310 [patent_doc_number] => 06415190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and device for executing by a single processor several functions of different criticality levels, operating with high security' [patent_app_type] => B1 [patent_app_number] => 09/380066 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415190.pdf [firstpage_image] =>[orig_patent_app_number] => 09380066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501329 [patent_doc_number] => 06405232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Leading bit prediction with in-parallel correction' [patent_app_type] => B1 [patent_app_number] => 09/377139 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405232.pdf [firstpage_image] =>[orig_patent_app_number] => 09377139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4290434 [patent_doc_number] => 06308256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Secure execution of program instructions provided by network interactions with processor' [patent_app_type] => 1 [patent_app_number] => 9/377297 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13027 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308256.pdf [firstpage_image] =>[orig_patent_app_number] => 377297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602056 [patent_doc_number] => 06385717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Programmable 1-bit data processing arrangement' [patent_app_type] => B1 [patent_app_number] => 09/375948 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385717.pdf [firstpage_image] =>[orig_patent_app_number] => 09375948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1584914 [patent_doc_number] => 06449714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution' [patent_app_type] => B1 [patent_app_number] => 09/375839 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 22360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449714.pdf [firstpage_image] =>[orig_patent_app_number] => 09375839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1592399 [patent_doc_number] => 06360315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method and apparatus that supports multiple assignment code' [patent_app_type] => B1 [patent_app_number] => 09/373516 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4173 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360315.pdf [firstpage_image] =>[orig_patent_app_number] => 09373516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280017 [patent_doc_number] => 06205533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Mechanism for efficient data access and communication in parallel computations on an emulated spatial lattice' [patent_app_type] => 1 [patent_app_number] => 9/373394 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14714 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205533.pdf [firstpage_image] =>[orig_patent_app_number] => 373394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567516 [patent_doc_number] => 06363476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Multiply-add operating device for floating point number' [patent_app_type] => B1 [patent_app_number] => 09/372135 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7507 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363476.pdf [firstpage_image] =>[orig_patent_app_number] => 09372135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513326 [patent_doc_number] => 06442675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Compressed string and multiple generation engine' [patent_app_type] => B1 [patent_app_number] => 09/363464 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442675.pdf [firstpage_image] =>[orig_patent_app_number] => 09363464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134165 [patent_doc_number] => 06792523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Processor with instructions that operate on different data types stored in the same single logical register file' [patent_app_type] => B1 [patent_app_number] => 09/363116 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 32742 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792523.pdf [firstpage_image] =>[orig_patent_app_number] => 09363116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1481793 [patent_doc_number] => 06345356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs' [patent_app_type] => B1 [patent_app_number] => 09/354498 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345356.pdf [firstpage_image] =>[orig_patent_app_number] => 09354498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557389 [patent_doc_number] => 06349392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Devices, systems and methods for mode driven stops' [patent_app_type] => B1 [patent_app_number] => 09/353520 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 37473 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349392.pdf [firstpage_image] =>[orig_patent_app_number] => 09353520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1539943 [patent_doc_number] => 06338099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Device code recognizing circuit' [patent_app_type] => B1 [patent_app_number] => 09/349376 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2499 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338099.pdf [firstpage_image] =>[orig_patent_app_number] => 09349376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255267 [patent_doc_number] => 06119218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for prefetching data in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/349839 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3809 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119218.pdf [firstpage_image] =>[orig_patent_app_number] => 349839 [rel_patent_id] =>[rel_patent_doc_number] =>)