Search

Vu A. Vu

Examiner (ID: 11603)

Most Active Art Unit
2828
Art Unit(s)
2823, 2897, 2828
Total Applications
1405
Issued Applications
1214
Pending Applications
128
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1432401 [patent_doc_number] => 06505293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Register renaming to optimize identical register values' [patent_app_type] => B1 [patent_app_number] => 09/348973 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7208 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505293.pdf [firstpage_image] =>[orig_patent_app_number] => 09348973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348973
Register renaming to optimize identical register values Jul 6, 1999 Issued
Array ( [id] => 1485084 [patent_doc_number] => 06453410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Computer system having a cache memory and a tracing function' [patent_app_type] => B1 [patent_app_number] => 09/348042 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7677 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453410.pdf [firstpage_image] =>[orig_patent_app_number] => 09348042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348042
Computer system having a cache memory and a tracing function Jul 5, 1999 Issued
Array ( [id] => 1501594 [patent_doc_number] => 06405301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Parallel data processing' [patent_app_type] => B1 [patent_app_number] => 09/333633 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8033 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405301.pdf [firstpage_image] =>[orig_patent_app_number] => 09333633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333633
Parallel data processing Jun 14, 1999 Issued
Array ( [id] => 4373895 [patent_doc_number] => 06202142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Microcode scan unit for scanning microcode instructions using predecode data' [patent_app_type] => 1 [patent_app_number] => 9/323301 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16939 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202142.pdf [firstpage_image] =>[orig_patent_app_number] => 323301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323301
Microcode scan unit for scanning microcode instructions using predecode data May 31, 1999 Issued
Array ( [id] => 4195234 [patent_doc_number] => 06085311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch' [patent_app_type] => 1 [patent_app_number] => 9/313847 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 3 [patent_no_of_words] => 12771 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085311.pdf [firstpage_image] =>[orig_patent_app_number] => 313847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313847
Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch May 17, 1999 Issued
09/194445 MICROCOMPUTER AND ELECTRONIC EQUIPMENT May 16, 1999 Abandoned
Array ( [id] => 6736977 [patent_doc_number] => 20030014612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'MULTI-THREADED PROCESSOR BY MULTIPLE-BIT FLIP-FLOP GLOBAL SUBSTITUTION' [patent_app_type] => new [patent_app_number] => 09/309730 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17658 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014612.pdf [firstpage_image] =>[orig_patent_app_number] => 09309730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309730
MULTI-THREADED PROCESSOR BY MULTIPLE-BIT FLIP-FLOP GLOBAL SUBSTITUTION May 10, 1999 Abandoned
Array ( [id] => 1495404 [patent_doc_number] => 06418531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Processor, loop program control device and multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/262332 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7690 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418531.pdf [firstpage_image] =>[orig_patent_app_number] => 09262332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262332
Processor, loop program control device and multiprocessor system Mar 3, 1999 Issued
Array ( [id] => 4085458 [patent_doc_number] => 06009513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Apparatus and method for detecting microbranches early' [patent_app_type] => 1 [patent_app_number] => 9/261116 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15696 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009513.pdf [firstpage_image] =>[orig_patent_app_number] => 261116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261116
Apparatus and method for detecting microbranches early Mar 2, 1999 Issued
Array ( [id] => 1443975 [patent_doc_number] => 06336183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'System and method for executing store instructions' [patent_app_type] => B1 [patent_app_number] => 09/259140 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3860 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336183.pdf [firstpage_image] =>[orig_patent_app_number] => 09259140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259140
System and method for executing store instructions Feb 25, 1999 Issued
Array ( [id] => 1434056 [patent_doc_number] => 06341346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method for comparison between a pattern sequence and a variable length key' [patent_app_type] => B1 [patent_app_number] => 09/245182 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3628 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341346.pdf [firstpage_image] =>[orig_patent_app_number] => 09245182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245182
Method for comparison between a pattern sequence and a variable length key Feb 4, 1999 Issued
Array ( [id] => 1513334 [patent_doc_number] => 06442678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for providing data to a processor pipeline' [patent_app_type] => B1 [patent_app_number] => 09/224412 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442678.pdf [firstpage_image] =>[orig_patent_app_number] => 09224412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224412
Method and apparatus for providing data to a processor pipeline Dec 30, 1998 Issued
Array ( [id] => 4400408 [patent_doc_number] => 06304955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method and apparatus for performing latency based hazard detection' [patent_app_type] => 1 [patent_app_number] => 9/223241 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6225 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304955.pdf [firstpage_image] =>[orig_patent_app_number] => 223241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223241
Method and apparatus for performing latency based hazard detection Dec 29, 1998 Issued
Array ( [id] => 4376919 [patent_doc_number] => 06219781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for performing register hazard detection' [patent_app_type] => 1 [patent_app_number] => 9/223240 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5414 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219781.pdf [firstpage_image] =>[orig_patent_app_number] => 223240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223240
Method and apparatus for performing register hazard detection Dec 29, 1998 Issued
Array ( [id] => 6693798 [patent_doc_number] => 20030041230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'METHOD AND SYSTEM FOR BRANCH TARGET PREDICTION USING PATH INFORMATION' [patent_app_type] => new [patent_app_number] => 09/223303 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10749 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041230.pdf [firstpage_image] =>[orig_patent_app_number] => 09223303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223303
Method and system for branch target prediction using path information Dec 29, 1998 Issued
Array ( [id] => 4298957 [patent_doc_number] => 06282636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Decentralized exception processing system' [patent_app_type] => 1 [patent_app_number] => 9/221197 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282636.pdf [firstpage_image] =>[orig_patent_app_number] => 221197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221197
Decentralized exception processing system Dec 22, 1998 Issued
Array ( [id] => 4423515 [patent_doc_number] => 06311266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Instruction look-ahead system and hardware' [patent_app_type] => 1 [patent_app_number] => 9/221187 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3892 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311266.pdf [firstpage_image] =>[orig_patent_app_number] => 221187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221187
Instruction look-ahead system and hardware Dec 22, 1998 Issued
09/217595 METHOD AND SYSTEM FOR GENERATING OBJECTS FOR A MULTI-PERSON VIRTUAL WORLD USING DATA FLOW NETWORKS Dec 21, 1998 Abandoned
Array ( [id] => 4124143 [patent_doc_number] => 06101592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Methods and apparatus for scalable instruction set architecture with dynamic compact instructions' [patent_app_type] => 1 [patent_app_number] => 9/215081 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101592.pdf [firstpage_image] =>[orig_patent_app_number] => 215081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215081
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions Dec 17, 1998 Issued
Array ( [id] => 4426666 [patent_doc_number] => 06178499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers' [patent_app_type] => 1 [patent_app_number] => 9/212143 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5934 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178499.pdf [firstpage_image] =>[orig_patent_app_number] => 212143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212143
Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers Dec 14, 1998 Issued
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