Vu A. Vu

Array ( [id] => 4766768 [patent_doc_number] => 20080177980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'INSTRUCTION SET ARCHITECTURE WITH OVERLAPPING FIELDS' [patent_app_type] => utility [patent_app_number] => 11/626380 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177980.pdf [firstpage_image] =>[orig_patent_app_number] => 11626380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4766777 [patent_doc_number] => 20080177989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'DEFINING MEMORY INDIFFERENT TRACE HANDLES' [patent_app_type] => utility [patent_app_number] => 11/625898 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177989.pdf [firstpage_image] =>[orig_patent_app_number] => 11625898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966826 [patent_doc_number] => 20080109646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'DATA PROCESSING APPARATUS FOR LOOP STRUCTURE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/624222 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2943 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109646.pdf [firstpage_image] =>[orig_patent_app_number] => 11624222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595786 [patent_doc_number] => 07620796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'System and method for acceleration of streams of dependent instructions within a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/653277 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5505 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620796.pdf [firstpage_image] =>[orig_patent_app_number] => 11653277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5190336 [patent_doc_number] => 20070168645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Methods and arrangements for conditional execution of instructions in parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/654065 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168645.pdf [firstpage_image] =>[orig_patent_app_number] => 11654065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4966825 [patent_doc_number] => 20080109645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'DATA PROCESSING APPARATUS FOR LOOP STRUCTURE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/623093 [patent_app_country] => US [patent_app_date] => 2007-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2942 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109645.pdf [firstpage_image] =>[orig_patent_app_number] => 11623093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 137275 [patent_doc_number] => 07698594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Reconfigurable processor and reconfiguration method executed by the reconfigurable processor' [patent_app_type] => utility [patent_app_number] => 11/622738 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5840 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698594.pdf [firstpage_image] =>[orig_patent_app_number] => 11622738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4808972 [patent_doc_number] => 20080172550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'METHOD AND CIRCUIT IMPLEMENTATION FOR MULTIPLE-WORD TRANSFER INTO/FROM MEMORY SUBSYSTEMS' [patent_app_type] => utility [patent_app_number] => 11/622471 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20080172550.pdf [firstpage_image] =>[orig_patent_app_number] => 11622471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 265531 [patent_doc_number] => 07571305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Reusing a buffer memory as a microcache for program instructions of a detected program loop' [patent_app_type] => utility [patent_app_number] => 11/652148 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3652 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571305.pdf [firstpage_image] =>[orig_patent_app_number] => 11652148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5248898 [patent_doc_number] => 20070245132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/621952 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12762 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245132.pdf [firstpage_image] =>[orig_patent_app_number] => 11621952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4454940 [patent_doc_number] => 07966475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Parallel data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/621946 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966475.pdf [firstpage_image] =>[orig_patent_app_number] => 11621946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4928895 [patent_doc_number] => 20080168258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform' [patent_app_type] => utility [patent_app_number] => 11/621393 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5133 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168258.pdf [firstpage_image] =>[orig_patent_app_number] => 11621393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 265526 [patent_doc_number] => 07571300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Modular distributive arithmetic logic unit' [patent_app_type] => utility [patent_app_number] => 11/621105 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571300.pdf [firstpage_image] =>[orig_patent_app_number] => 11621105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4928942 [patent_doc_number] => 20080168305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'SOFT ERROR HANDLING IN MICROPROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/620869 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2989 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168305.pdf [firstpage_image] =>[orig_patent_app_number] => 11620869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4928899 [patent_doc_number] => 20080168262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Methods and Apparatus for Software Control of a Non-Functional Operation on Memory' [patent_app_type] => utility [patent_app_number] => 11/620117 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9245 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168262.pdf [firstpage_image] =>[orig_patent_app_number] => 11620117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5248889 [patent_doc_number] => 20070245123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/620014 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12762 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245123.pdf [firstpage_image] =>[orig_patent_app_number] => 11620014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 245088 [patent_doc_number] => 07590832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Information processing device, compressed program producing method, and information processing system' [patent_app_type] => utility [patent_app_number] => 11/648627 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5559 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590832.pdf [firstpage_image] =>[orig_patent_app_number] => 11648627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4754822 [patent_doc_number] => 20080162898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'REGISTER MAP UNIT SUPPORTING MAPPING OF MULTIPLE REGISTER SPECIFIER CLASSES' [patent_app_type] => utility [patent_app_number] => 11/619248 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162898.pdf [firstpage_image] =>[orig_patent_app_number] => 11619248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 596404 [patent_doc_number] => 07454597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Computer processing system employing an instruction schedule cache' [patent_app_type] => utility [patent_app_number] => 11/618948 [patent_app_country] => US [patent_app_date] => 2007-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4695 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454597.pdf [firstpage_image] =>[orig_patent_app_number] => 11618948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 171872 [patent_doc_number] => 07669040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method and apparatus for executing a long transaction' [patent_app_type] => utility [patent_app_number] => 11/640018 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5964 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669040.pdf [firstpage_image] =>[orig_patent_app_number] => 11640018 [rel_patent_id] =>[rel_patent_doc_number] =>)