Vu A. Vu

Array ( [id] => 241372 [patent_doc_number] => 07594097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Microprocessor output ports and control of instructions provided therefrom' [patent_app_type] => utility [patent_app_number] => 11/632567 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594097.pdf [firstpage_image] =>[orig_patent_app_number] => 11632567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979612 [patent_doc_number] => 20050289330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Branch control method and information processor' [patent_app_type] => utility [patent_app_number] => 11/157920 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5704 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289330.pdf [firstpage_image] =>[orig_patent_app_number] => 11157920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979608 [patent_doc_number] => 20050289326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Packet processor with mild programmability' [patent_app_type] => utility [patent_app_number] => 11/158656 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289326.pdf [firstpage_image] =>[orig_patent_app_number] => 11158656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5689881 [patent_doc_number] => 20060288196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'System and method for exploiting timing variability in a processor pipeline' [patent_app_type] => utility [patent_app_number] => 11/157320 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5764 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20060288196.pdf [firstpage_image] =>[orig_patent_app_number] => 11157320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5689880 [patent_doc_number] => 20060288195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Apparatus and method for switchable conditional execution in a VLIW processor' [patent_app_type] => utility [patent_app_number] => 11/155120 [patent_app_country] => US [patent_app_date] => 2005-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20060288195.pdf [firstpage_image] =>[orig_patent_app_number] => 11155120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 379021 [patent_doc_number] => 07313675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Register allocation technique' [patent_app_type] => utility [patent_app_number] => 11/155755 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2917 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313675.pdf [firstpage_image] =>[orig_patent_app_number] => 11155755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 379017 [patent_doc_number] => 07313673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Fine grained multi-thread dispatch block mechanism' [patent_app_type] => utility [patent_app_number] => 11/154158 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313673.pdf [firstpage_image] =>[orig_patent_app_number] => 11154158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6953751 [patent_doc_number] => 20050228846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Magnitude comparator' [patent_app_type] => utility [patent_app_number] => 11/146591 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6583 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20050228846.pdf [firstpage_image] =>[orig_patent_app_number] => 11146591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7021569 [patent_doc_number] => 20050223195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Processor for making more efficient use of idling components and program conversion apparatus for the same' [patent_app_type] => utility [patent_app_number] => 11/144132 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7407 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223195.pdf [firstpage_image] =>[orig_patent_app_number] => 11144132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 469362 [patent_doc_number] => 07240183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method for detecting instruction dependencies in multiple phases' [patent_app_type] => utility [patent_app_number] => 11/140847 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7277 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240183.pdf [firstpage_image] =>[orig_patent_app_number] => 11140847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5822283 [patent_doc_number] => 20060026596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Context scheduling' [patent_app_type] => utility [patent_app_number] => 11/141993 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3004 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026596.pdf [firstpage_image] =>[orig_patent_app_number] => 11141993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7021583 [patent_doc_number] => 20050223205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Early exception detection' [patent_app_type] => utility [patent_app_number] => 11/135862 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2689 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223205.pdf [firstpage_image] =>[orig_patent_app_number] => 11135862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7240954 [patent_doc_number] => 20050257029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core' [patent_app_type] => utility [patent_app_number] => 11/119598 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4308 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20050257029.pdf [firstpage_image] =>[orig_patent_app_number] => 11119598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6932557 [patent_doc_number] => 20050283592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Dynamically controlling execution of operations within a multi-operation instruction' [patent_app_type] => utility [patent_app_number] => 11/099231 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283592.pdf [firstpage_image] =>[orig_patent_app_number] => 11099231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 414782 [patent_doc_number] => 07284114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Video processing system with reconfigurable instructions' [patent_app_type] => utility [patent_app_number] => 11/099280 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7792 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/284/07284114.pdf [firstpage_image] =>[orig_patent_app_number] => 11099280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5071463 [patent_doc_number] => 20070192565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Semiconductor device and mobile phone using the same' [patent_app_type] => utility [patent_app_number] => 10/575784 [patent_app_country] => US [patent_app_date] => 2005-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15905 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192565.pdf [firstpage_image] =>[orig_patent_app_number] => 10575784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 581429 [patent_doc_number] => 07434898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Computer system, computer program, and addition method' [patent_app_type] => utility [patent_app_number] => 10/591846 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13976 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434898.pdf [firstpage_image] =>[orig_patent_app_number] => 10591846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5535259 [patent_doc_number] => 20090235047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Computer system for electronic data processing' [patent_app_type] => utility [patent_app_number] => 10/592925 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9249 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235047.pdf [firstpage_image] =>[orig_patent_app_number] => 10592925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 925055 [patent_doc_number] => 07320066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Branch predicting apparatus and branch predicting method' [patent_app_type] => utility [patent_app_number] => 11/065712 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 56 [patent_no_of_words] => 17053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320066.pdf [firstpage_image] =>[orig_patent_app_number] => 11065712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5621168 [patent_doc_number] => 20060190703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Programmable delayed dispatch in a multi-threaded pipeline' [patent_app_type] => utility [patent_app_number] => 11/065646 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190703.pdf [firstpage_image] =>[orig_patent_app_number] => 11065646 [rel_patent_id] =>[rel_patent_doc_number] =>)