Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1488642 [patent_doc_number] => 06366520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and system for controlling the slew rate of signals generated by open drain driver circuits' [patent_app_type] => B1 [patent_app_number] => 09/808727 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5607 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366520.pdf [firstpage_image] =>[orig_patent_app_number] => 09808727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808727
Method and system for controlling the slew rate of signals generated by open drain driver circuits Mar 13, 2001 Issued
Array ( [id] => 6423024 [patent_doc_number] => 20020126541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method and apparatus for processing commands in a queue coupled to a system or memory' [patent_app_type] => new [patent_app_number] => 09/803229 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126541.pdf [firstpage_image] =>[orig_patent_app_number] => 09803229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803229
Method and apparatus for processing commands in a queue coupled to a system or memory Mar 8, 2001 Issued
Array ( [id] => 6895680 [patent_doc_number] => 20010026470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Magnetic field element having a biasing magnetic layer structure' [patent_app_type] => new [patent_app_number] => 09/801629 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4396 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026470.pdf [firstpage_image] =>[orig_patent_app_number] => 09801629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801629
Magnetic field element having a biasing magnetic layer structure Mar 7, 2001 Issued
Array ( [id] => 7630503 [patent_doc_number] => 06636433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Electronic device and recording method using the same' [patent_app_type] => B2 [patent_app_number] => 09/801325 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 46 [patent_no_of_words] => 7092 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636433.pdf [firstpage_image] =>[orig_patent_app_number] => 09801325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801325
Electronic device and recording method using the same Mar 6, 2001 Issued
Array ( [id] => 1570429 [patent_doc_number] => 06377513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for writing data to semiconductor memory and semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/763627 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8526 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377513.pdf [firstpage_image] =>[orig_patent_app_number] => 09763627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/763627
Method for writing data to semiconductor memory and semiconductor memory Mar 5, 2001 Issued
Array ( [id] => 6876325 [patent_doc_number] => 20010006478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell' [patent_app_type] => new-utility [patent_app_number] => 09/794041 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10472 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006478.pdf [firstpage_image] =>[orig_patent_app_number] => 09794041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794041
Electrically alterable non-volatile memory with n-bits per cell Feb 27, 2001 Issued
Array ( [id] => 6947505 [patent_doc_number] => 20010021139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Semiconductor register element' [patent_app_type] => new [patent_app_number] => 09/791729 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6929 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021139.pdf [firstpage_image] =>[orig_patent_app_number] => 09791729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791729
Semiconductor register element Feb 25, 2001 Issued
Array ( [id] => 6891628 [patent_doc_number] => 20010017790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Synchronous semiconductor memeory device and method for reading data' [patent_app_type] => new [patent_app_number] => 09/789729 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5827 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017790.pdf [firstpage_image] =>[orig_patent_app_number] => 09789729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789729
Synchronous semiconductor memory device and method for reading data Feb 21, 2001 Issued
Array ( [id] => 6897983 [patent_doc_number] => 20010046148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Single deposition layer metal dynamic random access memory' [patent_app_type] => new [patent_app_number] => 09/790425 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7302 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046148.pdf [firstpage_image] =>[orig_patent_app_number] => 09790425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790425
Single deposition layer metal dynamic random access memory Feb 20, 2001 Issued
Array ( [id] => 1511334 [patent_doc_number] => 06442064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Magnetic tunnel junction element and magnetic memory using the same' [patent_app_type] => B1 [patent_app_number] => 09/785635 [patent_app_country] => US [patent_app_date] => 2001-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5798 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442064.pdf [firstpage_image] =>[orig_patent_app_number] => 09785635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785635
Magnetic tunnel junction element and magnetic memory using the same Feb 16, 2001 Issued
Array ( [id] => 1546948 [patent_doc_number] => 06373775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor memory device with restrained scale of decoding circuit used in shift redundancy' [patent_app_type] => B1 [patent_app_number] => 09/784135 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 9915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373775.pdf [firstpage_image] =>[orig_patent_app_number] => 09784135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784135
Semiconductor memory device with restrained scale of decoding circuit used in shift redundancy Feb 15, 2001 Issued
Array ( [id] => 1570404 [patent_doc_number] => 06377506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/783431 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 49 [patent_no_of_words] => 44476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377506.pdf [firstpage_image] =>[orig_patent_app_number] => 09783431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783431
Semiconductor device Feb 13, 2001 Issued
Array ( [id] => 1473318 [patent_doc_number] => 06407954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/781829 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407954.pdf [firstpage_image] =>[orig_patent_app_number] => 09781829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781829
Nonvolatile semiconductor memory device Feb 11, 2001 Issued
Array ( [id] => 5998452 [patent_doc_number] => 20020027808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Differential output circuit' [patent_app_type] => new [patent_app_number] => 09/779825 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7152 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027808.pdf [firstpage_image] =>[orig_patent_app_number] => 09779825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779825
Differential output circuit Feb 8, 2001 Issued
Array ( [id] => 1493336 [patent_doc_number] => 06418053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Piggyback programming using graduated steps for multi-level cell flash memory designs' [patent_app_type] => B1 [patent_app_number] => 09/779225 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4121 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418053.pdf [firstpage_image] =>[orig_patent_app_number] => 09779225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779225
Piggyback programming using graduated steps for multi-level cell flash memory designs Feb 7, 2001 Issued
Array ( [id] => 4341800 [patent_doc_number] => 06320786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of controlling multi-state NROM' [patent_app_type] => 1 [patent_app_number] => 9/777229 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2179 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320786.pdf [firstpage_image] =>[orig_patent_app_number] => 777229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777229
Method of controlling multi-state NROM Feb 4, 2001 Issued
Array ( [id] => 6094353 [patent_doc_number] => 20020051395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Dynamic register with low clock rate testing capability' [patent_app_type] => new [patent_app_number] => 09/775243 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051395.pdf [firstpage_image] =>[orig_patent_app_number] => 09775243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775243
Dynamic register with low clock rate testing capability Jan 31, 2001 Issued
Array ( [id] => 6878017 [patent_doc_number] => 20010002172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => new-utility [patent_app_number] => 09/767152 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 45504 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002172.pdf [firstpage_image] =>[orig_patent_app_number] => 09767152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767152
Nonvolatile semiconductor memory device Jan 22, 2001 Issued
Array ( [id] => 4342066 [patent_doc_number] => 06320805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor device with external pins' [patent_app_type] => 1 [patent_app_number] => 9/767135 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3667 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320805.pdf [firstpage_image] =>[orig_patent_app_number] => 767135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767135
Semiconductor device with external pins Jan 22, 2001 Issued
Array ( [id] => 7027343 [patent_doc_number] => 20010014043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'MRAD test circuit, semiconductor memory device having the same and MRAD test method' [patent_app_type] => new [patent_app_number] => 09/766733 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3093 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014043.pdf [firstpage_image] =>[orig_patent_app_number] => 09766733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766733
MRAD test circuit, semiconductor memory device having the same and MRAD test method Jan 21, 2001 Issued
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