Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7027339 [patent_doc_number] => 20010014040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Semiconductor memory device having program circuit' [patent_app_type] => new [patent_app_number] => 09/765427 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 20833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014040.pdf [firstpage_image] =>[orig_patent_app_number] => 09765427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765427
Semiconductor memory device having program circuit Jan 21, 2001 Issued
Array ( [id] => 6899848 [patent_doc_number] => 20010009524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Semiconductor device having a test circuit' [patent_app_type] => new [patent_app_number] => 09/761727 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6076 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009524.pdf [firstpage_image] =>[orig_patent_app_number] => 09761727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761727
Semiconductor device having a test circuit Jan 17, 2001 Issued
Array ( [id] => 6921104 [patent_doc_number] => 20010028589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Self-refresh controlling apparatus' [patent_app_type] => new [patent_app_number] => 09/745427 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2050 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028589.pdf [firstpage_image] =>[orig_patent_app_number] => 09745427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745427
Self-refresh controlling apparatus Dec 25, 2000 Issued
Array ( [id] => 6876327 [patent_doc_number] => 20010006480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Multilevel storage semiconductor memory read circuit' [patent_app_type] => new-utility [patent_app_number] => 09/748035 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7159 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006480.pdf [firstpage_image] =>[orig_patent_app_number] => 09748035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748035
Multilevel storage semiconductor memory read circuit Dec 21, 2000 Issued
Array ( [id] => 4283495 [patent_doc_number] => 06307805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'High performance semiconductor memory device with low power consumption' [patent_app_type] => 1 [patent_app_number] => 9/745227 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4571 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307805.pdf [firstpage_image] =>[orig_patent_app_number] => 745227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745227
High performance semiconductor memory device with low power consumption Dec 20, 2000 Issued
Array ( [id] => 6400251 [patent_doc_number] => 20020036915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Ferroelectric memory' [patent_app_type] => new [patent_app_number] => 09/741029 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3890 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036915.pdf [firstpage_image] =>[orig_patent_app_number] => 09741029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741029
Ferroelectric memory Dec 20, 2000 Issued
Array ( [id] => 7105069 [patent_doc_number] => 20010004334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Method for operating a current sense amplifier' [patent_app_type] => new-utility [patent_app_number] => 09/742133 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1455 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004334.pdf [firstpage_image] =>[orig_patent_app_number] => 09742133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742133
Method for operating a current sense amplifier Dec 19, 2000 Issued
Array ( [id] => 6901170 [patent_doc_number] => 20010022753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Circuit and method for timing multi-level non-volatile memories' [patent_app_type] => new [patent_app_number] => 09/738889 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022753.pdf [firstpage_image] =>[orig_patent_app_number] => 09738889 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738889
Circuit and method for timing multi-level non-volatile memories Dec 14, 2000 Issued
Array ( [id] => 7644637 [patent_doc_number] => 06473336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Magnetic memory device' [patent_app_type] => B2 [patent_app_number] => 09/735629 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 41 [patent_no_of_words] => 18379 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473336.pdf [firstpage_image] =>[orig_patent_app_number] => 09735629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735629
Magnetic memory device Dec 13, 2000 Issued
Array ( [id] => 7064215 [patent_doc_number] => 20010043501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Redundancy circuitry for repairing defects in packaged memory having registers' [patent_app_type] => new [patent_app_number] => 09/734581 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2467 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043501.pdf [firstpage_image] =>[orig_patent_app_number] => 09734581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734581
Redundancy circuitry for repairing defects in packaged memory having registers Dec 12, 2000 Issued
Array ( [id] => 7064199 [patent_doc_number] => 20010043485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Integrated circuit with efficient testing arrangement' [patent_app_type] => new [patent_app_number] => 09/734925 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7166 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043485.pdf [firstpage_image] =>[orig_patent_app_number] => 09734925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734925
Integrated circuit with efficient testing arrangement Dec 12, 2000 Issued
Array ( [id] => 1433802 [patent_doc_number] => 06341092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Designing memory for testability to support scan capability in an asic design' [patent_app_type] => B1 [patent_app_number] => 09/735233 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4758 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341092.pdf [firstpage_image] =>[orig_patent_app_number] => 09735233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735233
Designing memory for testability to support scan capability in an asic design Dec 10, 2000 Issued
Array ( [id] => 6899846 [patent_doc_number] => 20010009522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Margin-range apparatus for a sense amp\'s voltage-pulling transistor' [patent_app_type] => new [patent_app_number] => 09/735120 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7305 [patent_no_of_claims] => 138 [patent_no_of_ind_claims] => 43 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009522.pdf [firstpage_image] =>[orig_patent_app_number] => 09735120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735120
Margin-range apparatus for a sense amp's voltage-pulling transistor Dec 10, 2000 Issued
Array ( [id] => 1550304 [patent_doc_number] => 06445629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method of stressing a memory device' [patent_app_type] => B1 [patent_app_number] => 09/735330 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7333 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445629.pdf [firstpage_image] =>[orig_patent_app_number] => 09735330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735330
Method of stressing a memory device Dec 10, 2000 Issued
Array ( [id] => 1578360 [patent_doc_number] => 06469944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method of compensating for a defect within a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/735119 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7335 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469944.pdf [firstpage_image] =>[orig_patent_app_number] => 09735119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735119
Method of compensating for a defect within a semiconductor device Dec 10, 2000 Issued
Array ( [id] => 1525639 [patent_doc_number] => 06353564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of testing a memory array' [patent_app_type] => B1 [patent_app_number] => 09/735157 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7335 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353564.pdf [firstpage_image] =>[orig_patent_app_number] => 09735157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735157
Method of testing a memory array Dec 10, 2000 Issued
Array ( [id] => 6877402 [patent_doc_number] => 20010002888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'METHOD OF TESTING A MEMORY CELL' [patent_app_type] => new-utility [patent_app_number] => 09/735329 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7304 [patent_no_of_claims] => 138 [patent_no_of_ind_claims] => 43 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002888.pdf [firstpage_image] =>[orig_patent_app_number] => 09735329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735329
Method of testing a memory cell Dec 10, 2000 Issued
Array ( [id] => 1482925 [patent_doc_number] => 06452846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Driver circuit for a voltage-pulling device' [patent_app_type] => B1 [patent_app_number] => 09/733434 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7332 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452846.pdf [firstpage_image] =>[orig_patent_app_number] => 09733434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733434
Driver circuit for a voltage-pulling device Dec 7, 2000 Issued
Array ( [id] => 4341924 [patent_doc_number] => 06320795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Pseudo-static leakage-tolerant register file bit-cell circuit' [patent_app_type] => 1 [patent_app_number] => 9/733225 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3840 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320795.pdf [firstpage_image] =>[orig_patent_app_number] => 733225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733225
Pseudo-static leakage-tolerant register file bit-cell circuit Dec 7, 2000 Issued
Array ( [id] => 6507060 [patent_doc_number] => 20020191439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Low voltage single supply cmos electrically erasable read-only memory' [patent_app_type] => new [patent_app_number] => 09/731099 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17302 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20020191439.pdf [firstpage_image] =>[orig_patent_app_number] => 09731099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731099
Low voltage single supply CMOS electrically erasable read-only memory Dec 4, 2000 Issued
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