Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4329771 [patent_doc_number] => 06331961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'DRAM based refresh-free ternary CAM' [patent_app_type] => 1 [patent_app_number] => 9/591033 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331961.pdf [firstpage_image] =>[orig_patent_app_number] => 591033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591033
DRAM based refresh-free ternary CAM Jun 8, 2000 Issued
Array ( [id] => 4327149 [patent_doc_number] => 06243283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Impedance control using fuses' [patent_app_type] => 1 [patent_app_number] => 9/589922 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 11945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243283.pdf [firstpage_image] =>[orig_patent_app_number] => 589922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/589922
Impedance control using fuses Jun 6, 2000 Issued
Array ( [id] => 4283013 [patent_doc_number] => 06307771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Integrated memory having 2-transistor/2-capacitor memory cells' [patent_app_type] => 1 [patent_app_number] => 9/584329 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2157 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307771.pdf [firstpage_image] =>[orig_patent_app_number] => 584329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584329
Integrated memory having 2-transistor/2-capacitor memory cells May 29, 2000 Issued
Array ( [id] => 4309091 [patent_doc_number] => 06198660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Synchronous multilevel non-volatile memory and related reading method' [patent_app_type] => 1 [patent_app_number] => 9/572127 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198660.pdf [firstpage_image] =>[orig_patent_app_number] => 572127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572127
Synchronous multilevel non-volatile memory and related reading method May 16, 2000 Issued
Array ( [id] => 7642952 [patent_doc_number] => 06430094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for testing a memory device having two or more memory arrays' [patent_app_type] => B1 [patent_app_number] => 09/571206 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5295 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430094.pdf [firstpage_image] =>[orig_patent_app_number] => 09571206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571206
Method for testing a memory device having two or more memory arrays May 15, 2000 Issued
Array ( [id] => 4374156 [patent_doc_number] => 06256246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/566789 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 52 [patent_no_of_words] => 11149 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256246.pdf [firstpage_image] =>[orig_patent_app_number] => 566789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566789
Semiconductor memory device May 7, 2000 Issued
Array ( [id] => 7644644 [patent_doc_number] => 06473329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor memory and method for accessing semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/530727 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473329.pdf [firstpage_image] =>[orig_patent_app_number] => 09530727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/530727
Semiconductor memory and method for accessing semiconductor memory May 3, 2000 Issued
Array ( [id] => 1488537 [patent_doc_number] => 06366488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Ferroelectric non-volatile memory cell integrated in a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/561331 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1422 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366488.pdf [firstpage_image] =>[orig_patent_app_number] => 09561331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561331
Ferroelectric non-volatile memory cell integrated in a semiconductor substrate Apr 27, 2000 Issued
Array ( [id] => 4327172 [patent_doc_number] => 06243285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'ROM-embedded-DRAM' [patent_app_type] => 1 [patent_app_number] => 9/559832 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 4378 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243285.pdf [firstpage_image] =>[orig_patent_app_number] => 559832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559832
ROM-embedded-DRAM Apr 27, 2000 Issued
Array ( [id] => 4384480 [patent_doc_number] => 06288957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory device having test mode and method for testing semiconductor therewith' [patent_app_type] => 1 [patent_app_number] => 9/556027 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 53 [patent_no_of_words] => 9813 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288957.pdf [firstpage_image] =>[orig_patent_app_number] => 556027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556027
Semiconductor memory device having test mode and method for testing semiconductor therewith Apr 19, 2000 Issued
Array ( [id] => 1418886 [patent_doc_number] => 06535431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory device' [patent_app_type] => B1 [patent_app_number] => 09/552933 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3674 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535431.pdf [firstpage_image] =>[orig_patent_app_number] => 09552933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552933
Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory device Apr 19, 2000 Issued
Array ( [id] => 4393898 [patent_doc_number] => 06295237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Semiconductor memory configuration with a built-in-self-test' [patent_app_type] => 1 [patent_app_number] => 9/553127 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3125 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295237.pdf [firstpage_image] =>[orig_patent_app_number] => 553127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553127
Semiconductor memory configuration with a built-in-self-test Apr 18, 2000 Issued
Array ( [id] => 6155739 [patent_doc_number] => 20020145928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Sense amplifier having integrated y multiplexor and method therefor' [patent_app_type] => new [patent_app_number] => 09/543131 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3721 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145928.pdf [firstpage_image] =>[orig_patent_app_number] => 09543131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543131
Sense amplifier having integrated y multiplexor and method therefor Apr 4, 2000 Issued
Array ( [id] => 4363968 [patent_doc_number] => 06215727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for utilizing parallel memory in a serial memory system' [patent_app_type] => 1 [patent_app_number] => 9/542633 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2512 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215727.pdf [firstpage_image] =>[orig_patent_app_number] => 542633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542633
Method and apparatus for utilizing parallel memory in a serial memory system Apr 3, 2000 Issued
Array ( [id] => 1488563 [patent_doc_number] => 06366497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and apparatus for low voltage sensing in flash memories' [patent_app_type] => B1 [patent_app_number] => 09/539725 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3182 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366497.pdf [firstpage_image] =>[orig_patent_app_number] => 09539725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539725
Method and apparatus for low voltage sensing in flash memories Mar 29, 2000 Issued
Array ( [id] => 4393221 [patent_doc_number] => 06304489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => 1 [patent_app_number] => 9/537933 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 24163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304489.pdf [firstpage_image] =>[orig_patent_app_number] => 537933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537933
Non-volatile semiconductor memory device and data programming method Mar 28, 2000 Issued
Array ( [id] => 4266040 [patent_doc_number] => 06208562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Digital memory and method of operation for a digital memory' [patent_app_type] => 1 [patent_app_number] => 9/536029 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3023 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208562.pdf [firstpage_image] =>[orig_patent_app_number] => 536029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536029
Digital memory and method of operation for a digital memory Mar 26, 2000 Issued
Array ( [id] => 4326543 [patent_doc_number] => 06317383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Detection circuit for detecting timing of two node signals' [patent_app_type] => 1 [patent_app_number] => 9/534533 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5025 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317383.pdf [firstpage_image] =>[orig_patent_app_number] => 534533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534533
Detection circuit for detecting timing of two node signals Mar 26, 2000 Issued
Array ( [id] => 4290885 [patent_doc_number] => 06282117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/532329 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 98 [patent_figures_cnt] => 124 [patent_no_of_words] => 64009 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282117.pdf [firstpage_image] =>[orig_patent_app_number] => 532329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532329
Nonvolatile semiconductor memory device Mar 20, 2000 Issued
Array ( [id] => 4202587 [patent_doc_number] => 06154419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory' [patent_app_type] => 1 [patent_app_number] => 9/524433 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4209 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154419.pdf [firstpage_image] =>[orig_patent_app_number] => 524433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524433
Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory Mar 12, 2000 Issued
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