Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4418480 [patent_doc_number] => 06310802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts' [patent_app_type] => 1 [patent_app_number] => 9/521933 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2298 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310802.pdf [firstpage_image] =>[orig_patent_app_number] => 521933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521933
Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts Mar 8, 2000 Issued
Array ( [id] => 4197140 [patent_doc_number] => 06160745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/515833 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11008 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160745.pdf [firstpage_image] =>[orig_patent_app_number] => 515833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515833
Semiconductor storage device Feb 28, 2000 Issued
Array ( [id] => 4318267 [patent_doc_number] => 06327216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Full page increment/decrement burst for DDR SDRAM/SGRAM' [patent_app_type] => 1 [patent_app_number] => 9/513641 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4783 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327216.pdf [firstpage_image] =>[orig_patent_app_number] => 513641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513641
Full page increment/decrement burst for DDR SDRAM/SGRAM Feb 24, 2000 Issued
Array ( [id] => 4416174 [patent_doc_number] => 06272033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Status bits for cache memory' [patent_app_type] => 1 [patent_app_number] => 9/512329 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3498 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272033.pdf [firstpage_image] =>[orig_patent_app_number] => 512329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512329
Status bits for cache memory Feb 23, 2000 Issued
Array ( [id] => 4419094 [patent_doc_number] => 06301153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/511915 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 14687 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301153.pdf [firstpage_image] =>[orig_patent_app_number] => 511915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511915
Nonvolatile semiconductor memory device Feb 22, 2000 Issued
Array ( [id] => 4266079 [patent_doc_number] => 06208565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Multi-ported register structure utilizing a pulse write mechanism' [patent_app_type] => 1 [patent_app_number] => 9/507333 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 12353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208565.pdf [firstpage_image] =>[orig_patent_app_number] => 507333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507333
Multi-ported register structure utilizing a pulse write mechanism Feb 17, 2000 Issued
Array ( [id] => 1590041 [patent_doc_number] => 06359830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Storage cell on integrated circuit responsive to plural frequency clocks' [patent_app_type] => B1 [patent_app_number] => 09/507327 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5884 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359830.pdf [firstpage_image] =>[orig_patent_app_number] => 09507327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507327
Storage cell on integrated circuit responsive to plural frequency clocks Feb 17, 2000 Issued
Array ( [id] => 4329697 [patent_doc_number] => 06331957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Integrated breakpoint detector and associated multi-level breakpoint techniques' [patent_app_type] => 1 [patent_app_number] => 9/503535 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6282 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331957.pdf [firstpage_image] =>[orig_patent_app_number] => 503535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503535
Integrated breakpoint detector and associated multi-level breakpoint techniques Feb 13, 2000 Issued
Array ( [id] => 1454327 [patent_doc_number] => 06456527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Nonvolatile multilevel memory and reading method thereof' [patent_app_type] => B1 [patent_app_number] => 09/501131 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456527.pdf [firstpage_image] =>[orig_patent_app_number] => 09501131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501131
Nonvolatile multilevel memory and reading method thereof Feb 8, 2000 Issued
Array ( [id] => 4298735 [patent_doc_number] => 06269045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Self-timed address decoder for register file and compare circuit of multi-port cam' [patent_app_type] => 1 [patent_app_number] => 9/500348 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 3200 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269045.pdf [firstpage_image] =>[orig_patent_app_number] => 500348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500348
Self-timed address decoder for register file and compare circuit of multi-port cam Feb 7, 2000 Issued
Array ( [id] => 4425606 [patent_doc_number] => 06195298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor integrated circuit capable of rapidly rewriting data into memory cells' [patent_app_type] => 1 [patent_app_number] => 9/499734 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 76 [patent_no_of_words] => 7431 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195298.pdf [firstpage_image] =>[orig_patent_app_number] => 499734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499734
Semiconductor integrated circuit capable of rapidly rewriting data into memory cells Feb 7, 2000 Issued
Array ( [id] => 4425636 [patent_doc_number] => 06195308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Self-timed address decoder for register file and compare circuit of a multi-port cam' [patent_app_type] => 1 [patent_app_number] => 9/500131 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 3198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195308.pdf [firstpage_image] =>[orig_patent_app_number] => 500131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500131
Self-timed address decoder for register file and compare circuit of a multi-port cam Feb 7, 2000 Issued
Array ( [id] => 4250381 [patent_doc_number] => 06144583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/497548 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 10738 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144583.pdf [firstpage_image] =>[orig_patent_app_number] => 497548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497548
Semiconductor integrated circuit device Feb 2, 2000 Issued
Array ( [id] => 4285019 [patent_doc_number] => 06246625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Semiconductor integrated circuit device having hierarchical power source arrangement' [patent_app_type] => 1 [patent_app_number] => 9/497199 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 67 [patent_no_of_words] => 48749 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246625.pdf [firstpage_image] =>[orig_patent_app_number] => 497199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497199
Semiconductor integrated circuit device having hierarchical power source arrangement Feb 2, 2000 Issued
Array ( [id] => 4418865 [patent_doc_number] => 06240030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated circuit devices having mode selection circuits that generate a mode signal based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state' [patent_app_type] => 1 [patent_app_number] => 9/496317 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5969 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240030.pdf [firstpage_image] =>[orig_patent_app_number] => 496317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496317
Integrated circuit devices having mode selection circuits that generate a mode signal based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state Jan 31, 2000 Issued
Array ( [id] => 1565066 [patent_doc_number] => 06362994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Memory architecture and decoder addressing' [patent_app_type] => B1 [patent_app_number] => 09/490933 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3632 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362994.pdf [firstpage_image] =>[orig_patent_app_number] => 09490933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/490933
Memory architecture and decoder addressing Jan 24, 2000 Issued
Array ( [id] => 4419024 [patent_doc_number] => 06240045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Synchronous semiconductor integrated circuit capable of improving immunity from malfunctions' [patent_app_type] => 1 [patent_app_number] => 9/489933 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 10814 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240045.pdf [firstpage_image] =>[orig_patent_app_number] => 489933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/489933
Synchronous semiconductor integrated circuit capable of improving immunity from malfunctions Jan 23, 2000 Issued
Array ( [id] => 4309257 [patent_doc_number] => 06181617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and apparatus for testing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/483549 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7214 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181617.pdf [firstpage_image] =>[orig_patent_app_number] => 483549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483549
Method and apparatus for testing a semiconductor device Jan 13, 2000 Issued
Array ( [id] => 4317077 [patent_doc_number] => 06188622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method of identifying a defect within a memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/483264 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7214 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188622.pdf [firstpage_image] =>[orig_patent_app_number] => 483264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483264
Method of identifying a defect within a memory circuit Jan 12, 2000 Issued
Array ( [id] => 4426410 [patent_doc_number] => 06226210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of detecting a short from a digit line pair to ground' [patent_app_type] => 1 [patent_app_number] => 9/482716 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226210.pdf [firstpage_image] =>[orig_patent_app_number] => 482716 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482716
Method of detecting a short from a digit line pair to ground Jan 11, 2000 Issued
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