Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4309309 [patent_doc_number] => 06198676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Test device' [patent_app_type] => 1 [patent_app_number] => 9/483266 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7210 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198676.pdf [firstpage_image] =>[orig_patent_app_number] => 483266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483266
Test device Jan 10, 2000 Issued
Array ( [id] => 4102471 [patent_doc_number] => 06134135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Mask arrangement for scalable CAM/RAM structures' [patent_app_type] => 1 [patent_app_number] => 9/480827 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2693 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134135.pdf [firstpage_image] =>[orig_patent_app_number] => 480827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480827
Mask arrangement for scalable CAM/RAM structures Jan 9, 2000 Issued
Array ( [id] => 4396796 [patent_doc_number] => 06262927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Current saturation test device' [patent_app_type] => 1 [patent_app_number] => 9/479347 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7212 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262927.pdf [firstpage_image] =>[orig_patent_app_number] => 479347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479347
Current saturation test device Jan 6, 2000 Issued
Array ( [id] => 4425583 [patent_doc_number] => 06178131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Magnetic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/479725 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2412 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178131.pdf [firstpage_image] =>[orig_patent_app_number] => 479725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479725
Magnetic random access memory Jan 6, 2000 Issued
Array ( [id] => 4318221 [patent_doc_number] => 06252813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Read only memory precharging circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/477223 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9439 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252813.pdf [firstpage_image] =>[orig_patent_app_number] => 477223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477223
Read only memory precharging circuit and method Jan 3, 2000 Issued
Array ( [id] => 4309902 [patent_doc_number] => 06185147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Programmable read only memory with high speed differential sensing at low operating voltage' [patent_app_type] => 1 [patent_app_number] => 9/478243 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9440 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185147.pdf [firstpage_image] =>[orig_patent_app_number] => 478243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478243
Programmable read only memory with high speed differential sensing at low operating voltage Jan 3, 2000 Issued
Array ( [id] => 4185409 [patent_doc_number] => 06141261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'DRAM that stores multiple bits per storage cell' [patent_app_type] => 1 [patent_app_number] => 9/476625 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2303 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141261.pdf [firstpage_image] =>[orig_patent_app_number] => 476625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476625
DRAM that stores multiple bits per storage cell Dec 30, 1999 Issued
Array ( [id] => 4185589 [patent_doc_number] => 06141273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Circuit for setting width of input/output data in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/475425 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141273.pdf [firstpage_image] =>[orig_patent_app_number] => 475425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475425
Circuit for setting width of input/output data in semiconductor memory device Dec 29, 1999 Issued
Array ( [id] => 4420094 [patent_doc_number] => 06266283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/472429 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266283.pdf [firstpage_image] =>[orig_patent_app_number] => 472429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472429
Semiconductor memory device Dec 26, 1999 Issued
Array ( [id] => 1499221 [patent_doc_number] => 06404680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Circuit to check overerasing of repair fuse cells' [patent_app_type] => B1 [patent_app_number] => 09/468933 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6572 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404680.pdf [firstpage_image] =>[orig_patent_app_number] => 09468933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468933
Circuit to check overerasing of repair fuse cells Dec 21, 1999 Issued
Array ( [id] => 4372267 [patent_doc_number] => 06191975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor' [patent_app_type] => 1 [patent_app_number] => 9/468333 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 2 [patent_no_of_words] => 17619 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191975.pdf [firstpage_image] =>[orig_patent_app_number] => 468333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468333
Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor Dec 20, 1999 Issued
Array ( [id] => 4197763 [patent_doc_number] => 06151252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/468316 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4734 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151252.pdf [firstpage_image] =>[orig_patent_app_number] => 468316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468316
Nonvolatile semiconductor memory device Dec 20, 1999 Issued
Array ( [id] => 4252151 [patent_doc_number] => 06166957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Nonvolatile semiconductor memory device with a level shifter circuit' [patent_app_type] => 1 [patent_app_number] => 9/465792 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166957.pdf [firstpage_image] =>[orig_patent_app_number] => 465792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465792
Nonvolatile semiconductor memory device with a level shifter circuit Dec 16, 1999 Issued
Array ( [id] => 1443039 [patent_doc_number] => 06335893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/446025 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 24490 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335893.pdf [firstpage_image] =>[orig_patent_app_number] => 09446025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/446025
Semiconductor integrated circuit device Dec 15, 1999 Issued
Array ( [id] => 4317045 [patent_doc_number] => 06188620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor memory device having a redundancy judgment circuit' [patent_app_type] => 1 [patent_app_number] => 9/457731 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5243 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188620.pdf [firstpage_image] =>[orig_patent_app_number] => 457731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457731
Semiconductor memory device having a redundancy judgment circuit Dec 9, 1999 Issued
Array ( [id] => 4384294 [patent_doc_number] => 06288945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics' [patent_app_type] => 1 [patent_app_number] => 9/457736 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 101 [patent_no_of_words] => 28272 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288945.pdf [firstpage_image] =>[orig_patent_app_number] => 457736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457736
Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics Dec 9, 1999 Issued
Array ( [id] => 4384539 [patent_doc_number] => 06288961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof' [patent_app_type] => 1 [patent_app_number] => 9/458094 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10165 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288961.pdf [firstpage_image] =>[orig_patent_app_number] => 458094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458094
Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof Dec 9, 1999 Issued
Array ( [id] => 4407154 [patent_doc_number] => 06297996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Test mode activation and data override' [patent_app_type] => 1 [patent_app_number] => 9/457558 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5681 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297996.pdf [firstpage_image] =>[orig_patent_app_number] => 457558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457558
Test mode activation and data override Dec 8, 1999 Issued
Array ( [id] => 4384414 [patent_doc_number] => 06288953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory device having sense amplifier control circuit responding to an address transition detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/457635 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288953.pdf [firstpage_image] =>[orig_patent_app_number] => 457635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457635
Semiconductor memory device having sense amplifier control circuit responding to an address transition detection circuit Dec 7, 1999 Issued
Array ( [id] => 4326515 [patent_doc_number] => 06317381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method and system for adaptively adjusting control signal timing in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/457429 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 5992 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317381.pdf [firstpage_image] =>[orig_patent_app_number] => 457429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457429
Method and system for adaptively adjusting control signal timing in a memory device Dec 6, 1999 Issued
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