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Array ( [id] => 4140336 [patent_doc_number] => 06128237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for enhancing the performance of semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/455365 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4476 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128237.pdf [firstpage_image] =>[orig_patent_app_number] => 455365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4283453 [patent_doc_number] => 06307802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Memory device with distributed voltage regulation system' [patent_app_type] => 1 [patent_app_number] => 9/454532 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3477 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307802.pdf [firstpage_image] =>[orig_patent_app_number] => 454532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418725 [patent_doc_number] => 06240018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Nonvolatile semiconductor memory device having verify function' [patent_app_type] => 1 [patent_app_number] => 9/451142 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 130 [patent_no_of_words] => 13787 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240018.pdf [firstpage_image] =>[orig_patent_app_number] => 451142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145213 [patent_doc_number] => 06147900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Spin dependent tunneling memory' [patent_app_type] => 1 [patent_app_number] => 9/449709 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 20773 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 457 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147900.pdf [firstpage_image] =>[orig_patent_app_number] => 449709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095801 [patent_doc_number] => 06163483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed' [patent_app_type] => 1 [patent_app_number] => 9/447531 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3880 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163483.pdf [firstpage_image] =>[orig_patent_app_number] => 447531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291382 [patent_doc_number] => 06282149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Circuit and method for synchronized data banking' [patent_app_type] => 1 [patent_app_number] => 9/448027 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5434 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282149.pdf [firstpage_image] =>[orig_patent_app_number] => 448027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252567 [patent_doc_number] => 06166987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Nonvolatile semiconductor memory device having row decoder' [patent_app_type] => 1 [patent_app_number] => 9/443100 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5956 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166987.pdf [firstpage_image] =>[orig_patent_app_number] => 443100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247493 [patent_doc_number] => 06118718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor memory device in which a BIT line pair having a high load is electrically separated from a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/440321 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5872 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118718.pdf [firstpage_image] =>[orig_patent_app_number] => 440321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153086 [patent_doc_number] => 06061285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Semiconductor memory device capable of executing earlier command operation in test mode' [patent_app_type] => 1 [patent_app_number] => 9/437729 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5016 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061285.pdf [firstpage_image] =>[orig_patent_app_number] => 437729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425601 [patent_doc_number] => 06195296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor memory device and system' [patent_app_type] => 1 [patent_app_number] => 9/437635 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8868 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195296.pdf [firstpage_image] =>[orig_patent_app_number] => 437635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302746 [patent_doc_number] => 06212119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Dynamic register with low clock rate testing capability' [patent_app_type] => 1 [patent_app_number] => 9/437723 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6966 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212119.pdf [firstpage_image] =>[orig_patent_app_number] => 437723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418669 [patent_doc_number] => 06310821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Clock-synchronous semiconductor memory device and access method thereof' [patent_app_type] => 1 [patent_app_number] => 9/435627 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6211 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310821.pdf [firstpage_image] =>[orig_patent_app_number] => 435627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380757 [patent_doc_number] => 06275411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Spin dependent tunneling memory' [patent_app_type] => 1 [patent_app_number] => 9/435598 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 19891 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275411.pdf [firstpage_image] =>[orig_patent_app_number] => 435598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363708 [patent_doc_number] => 06215710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Apparatus and method for controlling data strobe signal in DDR SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/428535 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2411 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215710.pdf [firstpage_image] =>[orig_patent_app_number] => 428535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152787 [patent_doc_number] => 06061268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => '0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique' [patent_app_type] => 1 [patent_app_number] => 9/427727 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1527 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061268.pdf [firstpage_image] =>[orig_patent_app_number] => 427727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417558 [patent_doc_number] => 06172921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Column redundancy circuit for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/426725 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4191 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172921.pdf [firstpage_image] =>[orig_patent_app_number] => 426725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131368 [patent_doc_number] => 06072736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/418021 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 7 [patent_no_of_words] => 8596 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072736.pdf [firstpage_image] =>[orig_patent_app_number] => 418021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114832 [patent_doc_number] => 06052302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Bit-wise conditional write method and system for an MRAM' [patent_app_type] => 1 [patent_app_number] => 9/406425 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6246 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052302.pdf [firstpage_image] =>[orig_patent_app_number] => 406425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4251738 [patent_doc_number] => 06091639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Non-volatile semiconductor memory device and data programming method' [patent_app_type] => 1 [patent_app_number] => 9/405282 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 24152 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091639.pdf [firstpage_image] =>[orig_patent_app_number] => 405282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159484 [patent_doc_number] => 06064602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'High-performance pass-gate isolation circuitry' [patent_app_type] => 1 [patent_app_number] => 9/399922 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3423 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064602.pdf [firstpage_image] =>[orig_patent_app_number] => 399922 [rel_patent_id] =>[rel_patent_doc_number] =>)