Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4097251 [patent_doc_number] => 06026053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Photorefractive read-only optical memory apparatus using phase, frequency, and angular modulation' [patent_app_type] => 1 [patent_app_number] => 9/316031 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9156 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026053.pdf [firstpage_image] =>[orig_patent_app_number] => 316031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316031
Photorefractive read-only optical memory apparatus using phase, frequency, and angular modulation May 20, 1999 Issued
Array ( [id] => 4230799 [patent_doc_number] => 06041014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Nonvolatile semiconductor memory device having row decoder' [patent_app_type] => 1 [patent_app_number] => 9/307709 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5957 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041014.pdf [firstpage_image] =>[orig_patent_app_number] => 307709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307709
Nonvolatile semiconductor memory device having row decoder May 9, 1999 Issued
Array ( [id] => 4093547 [patent_doc_number] => 06055195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Delay circuit and delay chain circuit for measurement of the charge/discharge period of dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/306131 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4943 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055195.pdf [firstpage_image] =>[orig_patent_app_number] => 306131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306131
Delay circuit and delay chain circuit for measurement of the charge/discharge period of dynamic random access memory May 5, 1999 Issued
Array ( [id] => 4185157 [patent_doc_number] => 06141245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Impedance control using fuses' [patent_app_type] => 1 [patent_app_number] => 9/302902 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 11951 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141245.pdf [firstpage_image] =>[orig_patent_app_number] => 302902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302902
Impedance control using fuses Apr 29, 1999 Issued
Array ( [id] => 4252540 [patent_doc_number] => 06166985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Integrated circuit low leakage power circuitry for use with an advanced CMOS process' [patent_app_type] => 1 [patent_app_number] => 9/302729 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5446 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166985.pdf [firstpage_image] =>[orig_patent_app_number] => 302729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302729
Integrated circuit low leakage power circuitry for use with an advanced CMOS process Apr 29, 1999 Issued
Array ( [id] => 4171773 [patent_doc_number] => 06115313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for saving data in the event of unwanted interruptions in the programming cycle of a nonvolatile memory, and a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/302231 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5197 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115313.pdf [firstpage_image] =>[orig_patent_app_number] => 302231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302231
Method for saving data in the event of unwanted interruptions in the programming cycle of a nonvolatile memory, and a nonvolatile memory Apr 28, 1999 Issued
Array ( [id] => 4185348 [patent_doc_number] => 06141257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Device for the configuration of options in an integrated circuit and implementation method' [patent_app_type] => 1 [patent_app_number] => 9/301505 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3440 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141257.pdf [firstpage_image] =>[orig_patent_app_number] => 301505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301505
Device for the configuration of options in an integrated circuit and implementation method Apr 27, 1999 Issued
Array ( [id] => 4219071 [patent_doc_number] => 06028784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Ferroelectric memory device having compact memory cell array' [patent_app_type] => 1 [patent_app_number] => 9/300931 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7422 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028784.pdf [firstpage_image] =>[orig_patent_app_number] => 300931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300931
Ferroelectric memory device having compact memory cell array Apr 27, 1999 Issued
Array ( [id] => 4231549 [patent_doc_number] => 06088279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor memory device with dummy word line' [patent_app_type] => 1 [patent_app_number] => 9/300004 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3303 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088279.pdf [firstpage_image] =>[orig_patent_app_number] => 300004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300004
Semiconductor memory device with dummy word line Apr 25, 1999 Issued
Array ( [id] => 4309831 [patent_doc_number] => 06185142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Apparatus for a semiconductor memory with independent reference voltage' [patent_app_type] => 1 [patent_app_number] => 9/296902 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4056 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185142.pdf [firstpage_image] =>[orig_patent_app_number] => 296902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296902
Apparatus for a semiconductor memory with independent reference voltage Apr 21, 1999 Issued
Array ( [id] => 4155182 [patent_doc_number] => 06031765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Reversed split-gate cell array' [patent_app_type] => 1 [patent_app_number] => 9/298032 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4575 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031765.pdf [firstpage_image] =>[orig_patent_app_number] => 298032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298032
Reversed split-gate cell array Apr 21, 1999 Issued
Array ( [id] => 4197050 [patent_doc_number] => 06160739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Non-volatile memories with improved endurance and extended lifetime' [patent_app_type] => 1 [patent_app_number] => 9/293133 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8476 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160739.pdf [firstpage_image] =>[orig_patent_app_number] => 293133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293133
Non-volatile memories with improved endurance and extended lifetime Apr 15, 1999 Issued
Array ( [id] => 4309244 [patent_doc_number] => 06181616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test' [patent_app_type] => 1 [patent_app_number] => 9/293203 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5274 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181616.pdf [firstpage_image] =>[orig_patent_app_number] => 293203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293203
Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test Apr 15, 1999 Issued
Array ( [id] => 4325992 [patent_doc_number] => 06317349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Non-volatile content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/293134 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11540 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317349.pdf [firstpage_image] =>[orig_patent_app_number] => 293134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293134
Non-volatile content addressable memory Apr 15, 1999 Issued
Array ( [id] => 4131091 [patent_doc_number] => 06072716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Memory structures and methods of making same' [patent_app_type] => 1 [patent_app_number] => 9/291801 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5314 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072716.pdf [firstpage_image] =>[orig_patent_app_number] => 291801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291801
Memory structures and methods of making same Apr 13, 1999 Issued
Array ( [id] => 4367933 [patent_doc_number] => 06201740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Cache memories using DRAM cells with high-speed data path' [patent_app_type] => 1 [patent_app_number] => 9/291536 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3520 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201740.pdf [firstpage_image] =>[orig_patent_app_number] => 291536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291536
Cache memories using DRAM cells with high-speed data path Apr 13, 1999 Issued
Array ( [id] => 4250714 [patent_doc_number] => 06081467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath' [patent_app_type] => 1 [patent_app_number] => 9/289875 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5191 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081467.pdf [firstpage_image] =>[orig_patent_app_number] => 289875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289875
Memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath Apr 11, 1999 Issued
Array ( [id] => 4120633 [patent_doc_number] => 06058057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Timing generator for semiconductor test system' [patent_app_type] => 1 [patent_app_number] => 9/289201 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058057.pdf [firstpage_image] =>[orig_patent_app_number] => 289201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289201
Timing generator for semiconductor test system Apr 8, 1999 Issued
Array ( [id] => 4116909 [patent_doc_number] => 06101123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Nonvolatile semiconductor memory with programming and erasing verification' [patent_app_type] => 1 [patent_app_number] => 9/288313 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 13832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101123.pdf [firstpage_image] =>[orig_patent_app_number] => 288313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288313
Nonvolatile semiconductor memory with programming and erasing verification Apr 7, 1999 Issued
Array ( [id] => 4110838 [patent_doc_number] => 06067263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Dynamic random access memory circuit having a testing system and method to determine the sensitivity of a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/287803 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4569 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067263.pdf [firstpage_image] =>[orig_patent_app_number] => 287803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287803
Dynamic random access memory circuit having a testing system and method to determine the sensitivity of a sense amplifier Apr 6, 1999 Issued
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