Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4202482 [patent_doc_number] => 06154413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for designing a memory tile for use in a tiled memory' [patent_app_type] => 1 [patent_app_number] => 9/286201 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 9165 [patent_no_of_claims] => 244 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154413.pdf [firstpage_image] =>[orig_patent_app_number] => 286201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286201
Method for designing a memory tile for use in a tiled memory Apr 4, 1999 Issued
Array ( [id] => 4372355 [patent_doc_number] => 06191981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Sense amp control circuit' [patent_app_type] => 1 [patent_app_number] => 9/283575 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2280 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191981.pdf [firstpage_image] =>[orig_patent_app_number] => 283575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283575
Sense amp control circuit Mar 31, 1999 Issued
Array ( [id] => 4095686 [patent_doc_number] => 06163475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Bit line cross-over layout arrangement' [patent_app_type] => 1 [patent_app_number] => 9/285232 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 47 [patent_no_of_words] => 74299 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163475.pdf [firstpage_image] =>[orig_patent_app_number] => 285232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285232
Bit line cross-over layout arrangement Mar 31, 1999 Issued
Array ( [id] => 4417437 [patent_doc_number] => 06172911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Non-volatile semiconductor memory device with an improved verify voltage generator' [patent_app_type] => 1 [patent_app_number] => 9/283583 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 99 [patent_figures_cnt] => 151 [patent_no_of_words] => 28765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172911.pdf [firstpage_image] =>[orig_patent_app_number] => 283583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283583
Non-volatile semiconductor memory device with an improved verify voltage generator Mar 31, 1999 Issued
Array ( [id] => 4204529 [patent_doc_number] => 06044009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'DRAM cell arrangement and method for its production' [patent_app_type] => 1 [patent_app_number] => 9/274733 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044009.pdf [firstpage_image] =>[orig_patent_app_number] => 274733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274733
DRAM cell arrangement and method for its production Mar 22, 1999 Issued
Array ( [id] => 4116895 [patent_doc_number] => 06101122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Data latch circuit' [patent_app_type] => 1 [patent_app_number] => 9/273488 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2449 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101122.pdf [firstpage_image] =>[orig_patent_app_number] => 273488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273488
Data latch circuit Mar 21, 1999 Issued
Array ( [id] => 4078033 [patent_doc_number] => 06009020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation' [patent_app_type] => 1 [patent_app_number] => 9/266731 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009020.pdf [firstpage_image] =>[orig_patent_app_number] => 266731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266731
Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation Mar 11, 1999 Issued
Array ( [id] => 4219500 [patent_doc_number] => 06028812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Semiconductor memory device and method for controlling the same' [patent_app_type] => 1 [patent_app_number] => 9/261734 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13153 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028812.pdf [firstpage_image] =>[orig_patent_app_number] => 261734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261734
Semiconductor memory device and method for controlling the same Mar 2, 1999 Issued
Array ( [id] => 4219297 [patent_doc_number] => 06028799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Memory circuit voltage regulator' [patent_app_type] => 1 [patent_app_number] => 9/260232 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7214 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028799.pdf [firstpage_image] =>[orig_patent_app_number] => 260232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260232
Memory circuit voltage regulator Feb 28, 1999 Issued
Array ( [id] => 3957433 [patent_doc_number] => 05982687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of detecting leakage within a memory cell capacitor' [patent_app_type] => 1 [patent_app_number] => 9/260236 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7185 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982687.pdf [firstpage_image] =>[orig_patent_app_number] => 260236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260236
Method of detecting leakage within a memory cell capacitor Feb 28, 1999 Issued
Array ( [id] => 4097034 [patent_doc_number] => 06026040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method of altering the margin affecting a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/259220 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7244 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026040.pdf [firstpage_image] =>[orig_patent_app_number] => 259220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259220
Method of altering the margin affecting a memory cell Feb 28, 1999 Issued
Array ( [id] => 3957417 [patent_doc_number] => 05982686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Memory circuit voltage regulator' [patent_app_type] => 1 [patent_app_number] => 9/259219 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7214 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982686.pdf [firstpage_image] =>[orig_patent_app_number] => 259219 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259219
Memory circuit voltage regulator Feb 28, 1999 Issued
Array ( [id] => 4234125 [patent_doc_number] => 06011731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Cell plate regulator' [patent_app_type] => 1 [patent_app_number] => 9/259221 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011731.pdf [firstpage_image] =>[orig_patent_app_number] => 259221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259221
Cell plate regulator Feb 28, 1999 Issued
Array ( [id] => 4417071 [patent_doc_number] => 06233199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Full page increment/decrement burst for DDR SDRAM/SGRAM' [patent_app_type] => 1 [patent_app_number] => 9/259034 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4445 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233199.pdf [firstpage_image] =>[orig_patent_app_number] => 259034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259034
Full page increment/decrement burst for DDR SDRAM/SGRAM Feb 25, 1999 Issued
Array ( [id] => 4234203 [patent_doc_number] => 06011736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Device and method for testing a circuit' [patent_app_type] => 1 [patent_app_number] => 9/258096 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011736.pdf [firstpage_image] =>[orig_patent_app_number] => 258096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258096
Device and method for testing a circuit Feb 24, 1999 Issued
Array ( [id] => 4187783 [patent_doc_number] => 06084806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/256135 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084806.pdf [firstpage_image] =>[orig_patent_app_number] => 256135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256135
Semiconductor memory device Feb 23, 1999 Issued
Array ( [id] => 3937304 [patent_doc_number] => 05946250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Memory testing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/252634 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2513 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946250.pdf [firstpage_image] =>[orig_patent_app_number] => 252634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252634
Memory testing apparatus Feb 18, 1999 Issued
Array ( [id] => 4086246 [patent_doc_number] => 05966328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Nonvolatile semiconductor memory device having a program area' [patent_app_type] => 1 [patent_app_number] => 9/252231 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5237 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966328.pdf [firstpage_image] =>[orig_patent_app_number] => 252231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252231
Nonvolatile semiconductor memory device having a program area Feb 17, 1999 Issued
Array ( [id] => 4197227 [patent_doc_number] => 06094383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Programmable non-volatile memory device and method of programming the same' [patent_app_type] => 1 [patent_app_number] => 9/251632 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2876 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094383.pdf [firstpage_image] =>[orig_patent_app_number] => 251632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251632
Programmable non-volatile memory device and method of programming the same Feb 16, 1999 Issued
Array ( [id] => 4086078 [patent_doc_number] => 05966317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Shielded bitlines for static RAMs' [patent_app_type] => 1 [patent_app_number] => 9/247633 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1739 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966317.pdf [firstpage_image] =>[orig_patent_app_number] => 247633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247633
Shielded bitlines for static RAMs Feb 9, 1999 Issued
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