Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4216856 [patent_doc_number] => 06078526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Flash memory with plural memory chips of same memory capacity and system utilizing the same' [patent_app_type] => 1 [patent_app_number] => 9/207034 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5630 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078526.pdf [firstpage_image] =>[orig_patent_app_number] => 207034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207034
Flash memory with plural memory chips of same memory capacity and system utilizing the same Dec 7, 1998 Issued
Array ( [id] => 4216994 [patent_doc_number] => 06078536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods' [patent_app_type] => 1 [patent_app_number] => 9/207534 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078536.pdf [firstpage_image] =>[orig_patent_app_number] => 207534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207534
Packet type integrated circuit memory devices having pins assigned direct test mode and associated methods Dec 7, 1998 Issued
Array ( [id] => 4096557 [patent_doc_number] => 06026009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Ferroelectric memory device increasing voltage on a bit line to remove dummy cells and a reference voltage generator' [patent_app_type] => 1 [patent_app_number] => 9/207033 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2694 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026009.pdf [firstpage_image] =>[orig_patent_app_number] => 207033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207033
Ferroelectric memory device increasing voltage on a bit line to remove dummy cells and a reference voltage generator Dec 7, 1998 Issued
Array ( [id] => 4155524 [patent_doc_number] => 06031788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/207335 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 12800 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031788.pdf [firstpage_image] =>[orig_patent_app_number] => 207335 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207335
Semiconductor integrated circuit Dec 7, 1998 Issued
Array ( [id] => 4216683 [patent_doc_number] => 06078515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Memory system with multiple addressing and control busses' [patent_app_type] => 1 [patent_app_number] => 9/196624 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 15 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078515.pdf [firstpage_image] =>[orig_patent_app_number] => 196624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196624
Memory system with multiple addressing and control busses Nov 17, 1998 Issued
Array ( [id] => 4116630 [patent_doc_number] => 06023438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof' [patent_app_type] => 1 [patent_app_number] => 9/193131 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 10166 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023438.pdf [firstpage_image] =>[orig_patent_app_number] => 193131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193131
Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof Nov 16, 1998 Issued
Array ( [id] => 4250519 [patent_doc_number] => 06144591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Redundancy selection circuit for semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 9/193239 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4013 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144591.pdf [firstpage_image] =>[orig_patent_app_number] => 193239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193239
Redundancy selection circuit for semiconductor memories Nov 16, 1998 Issued
Array ( [id] => 4078064 [patent_doc_number] => 06009022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Node-precise voltage regulation for a MOS memory system' [patent_app_type] => 1 [patent_app_number] => 9/189109 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 15349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009022.pdf [firstpage_image] =>[orig_patent_app_number] => 189109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189109
Node-precise voltage regulation for a MOS memory system Nov 8, 1998 Issued
Array ( [id] => 3937507 [patent_doc_number] => 05946264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and structure for enhancing the access time of integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 9/183231 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2796 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946264.pdf [firstpage_image] =>[orig_patent_app_number] => 183231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183231
Method and structure for enhancing the access time of integrated circuit memory devices Oct 29, 1998 Issued
Array ( [id] => 4045935 [patent_doc_number] => 05943277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Apparatus and method for recognizing the state of connection of terminals' [patent_app_type] => 1 [patent_app_number] => 9/182234 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9762 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943277.pdf [firstpage_image] =>[orig_patent_app_number] => 182234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182234
Apparatus and method for recognizing the state of connection of terminals Oct 29, 1998 Issued
Array ( [id] => 3970316 [patent_doc_number] => 05936906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Multilevel sense device for a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/183332 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936906.pdf [firstpage_image] =>[orig_patent_app_number] => 183332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183332
Multilevel sense device for a flash memory Oct 28, 1998 Issued
Array ( [id] => 3963905 [patent_doc_number] => 05978268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Circuit for the generation of voltage for the programming or erasure of a memory that uses floating-gate transistors' [patent_app_type] => 1 [patent_app_number] => 9/179635 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 4211 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978268.pdf [firstpage_image] =>[orig_patent_app_number] => 179635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179635
Circuit for the generation of voltage for the programming or erasure of a memory that uses floating-gate transistors Oct 26, 1998 Issued
Array ( [id] => 4017800 [patent_doc_number] => 06005825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Synchronous semiconductor memory device having wave pipelining control structure and method for outputting data using the same' [patent_app_type] => 1 [patent_app_number] => 9/178734 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3722 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005825.pdf [firstpage_image] =>[orig_patent_app_number] => 178734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178734
Synchronous semiconductor memory device having wave pipelining control structure and method for outputting data using the same Oct 26, 1998 Issued
Array ( [id] => 4131300 [patent_doc_number] => 06072731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/178831 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3729 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072731.pdf [firstpage_image] =>[orig_patent_app_number] => 178831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178831
Semiconductor memory circuit Oct 25, 1998 Issued
Array ( [id] => 4096285 [patent_doc_number] => 06018481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Dynamic semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/174534 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5145 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018481.pdf [firstpage_image] =>[orig_patent_app_number] => 174534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174534
Dynamic semiconductor memory device Oct 18, 1998 Issued
Array ( [id] => 4209333 [patent_doc_number] => 06014330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/167969 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 62 [patent_no_of_words] => 19993 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014330.pdf [firstpage_image] =>[orig_patent_app_number] => 167969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167969
Non-volatile semiconductor memory device Oct 7, 1998 Issued
Array ( [id] => 4116954 [patent_doc_number] => 06101126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Nonvolatile semiconductor memory device with a level shifter circuit' [patent_app_type] => 1 [patent_app_number] => 9/167534 [patent_app_country] => US [patent_app_date] => 1998-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3685 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101126.pdf [firstpage_image] =>[orig_patent_app_number] => 167534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167534
Nonvolatile semiconductor memory device with a level shifter circuit Oct 6, 1998 Issued
Array ( [id] => 4078257 [patent_doc_number] => 06009034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Memory device with distributed voltage regulation system' [patent_app_type] => 1 [patent_app_number] => 9/167042 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3521 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009034.pdf [firstpage_image] =>[orig_patent_app_number] => 167042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167042
Memory device with distributed voltage regulation system Oct 4, 1998 Issued
Array ( [id] => 4064752 [patent_doc_number] => 05969978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Read/write memory architecture employing closed ring elements' [patent_app_type] => 1 [patent_app_number] => 9/163333 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969978.pdf [firstpage_image] =>[orig_patent_app_number] => 163333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163333
Read/write memory architecture employing closed ring elements Sep 29, 1998 Issued
Array ( [id] => 4110176 [patent_doc_number] => 06097629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Non-volatile, static random access memory with high speed store capability' [patent_app_type] => 1 [patent_app_number] => 9/164531 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097629.pdf [firstpage_image] =>[orig_patent_app_number] => 164531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164531
Non-volatile, static random access memory with high speed store capability Sep 29, 1998 Issued
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