
Vu Anh Le
Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2825, 0, 2824, 2511 |
| Total Applications | 2999 |
| Issued Applications | 2864 |
| Pending Applications | 54 |
| Abandoned Applications | 89 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3970086
[patent_doc_number] => 05936891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/120742
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3139
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/936/05936891.pdf
[firstpage_image] =>[orig_patent_app_number] => 120742
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120742 | Non-volatile semiconductor memory device | Jul 22, 1998 | Issued |
Array
(
[id] => 4054518
[patent_doc_number] => 05912847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Semiconductor memory device having a save register for read data'
[patent_app_type] => 1
[patent_app_number] => 9/120738
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4161
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/912/05912847.pdf
[firstpage_image] =>[orig_patent_app_number] => 120738
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120738 | Semiconductor memory device having a save register for read data | Jul 22, 1998 | Issued |
Array
(
[id] => 4012490
[patent_doc_number] => 05986962
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Internal shadow latch'
[patent_app_type] => 1
[patent_app_number] => 9/121232
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3967
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/986/05986962.pdf
[firstpage_image] =>[orig_patent_app_number] => 121232
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121232 | Internal shadow latch | Jul 22, 1998 | Issued |
| 09/120739 | SEMICONDUCTOR MEMORY DEVICE HAVING BOOSTER SUPPLYING STEP-UP VOLTAGE EXCLUSIVELY TO OUTPUT CIRCUIT FOR BURST | Jul 22, 1998 | Issued |
Array
(
[id] => 3997866
[patent_doc_number] => 05959876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Single or dual message multilevel analog signal recording and playback system containing independently controlled signal storage segments with externally selectable duration capability'
[patent_app_type] => 1
[patent_app_number] => 9/115442
[patent_app_country] => US
[patent_app_date] => 1998-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 5199
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/959/05959876.pdf
[firstpage_image] =>[orig_patent_app_number] => 115442
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/115442 | Single or dual message multilevel analog signal recording and playback system containing independently controlled signal storage segments with externally selectable duration capability | Jul 13, 1998 | Issued |
Array
(
[id] => 585733
[patent_doc_number] => 07460399
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-02
[patent_title] => 'Flash EEprom system'
[patent_app_type] => utility
[patent_app_number] => 09/114504
[patent_app_country] => US
[patent_app_date] => 1998-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 9618
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/460/07460399.pdf
[firstpage_image] =>[orig_patent_app_number] => 09114504
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/114504 | Flash EEprom system | Jul 12, 1998 | Issued |
Array
(
[id] => 4026213
[patent_doc_number] => 05963502
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing'
[patent_app_type] => 1
[patent_app_number] => 9/112439
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 11278
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/963/05963502.pdf
[firstpage_image] =>[orig_patent_app_number] => 112439
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112439 | Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing | Jul 8, 1998 | Issued |
Array
(
[id] => 3947232
[patent_doc_number] => 05940333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Recursive voltage boosting technique'
[patent_app_type] => 1
[patent_app_number] => 9/111939
[patent_app_country] => US
[patent_app_date] => 1998-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3983
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/940/05940333.pdf
[firstpage_image] =>[orig_patent_app_number] => 111939
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111939 | Recursive voltage boosting technique | Jul 7, 1998 | Issued |
Array
(
[id] => 3970116
[patent_doc_number] => 05936893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Integrated circuit clock input buffer'
[patent_app_type] => 1
[patent_app_number] => 9/109632
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2995
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/936/05936893.pdf
[firstpage_image] =>[orig_patent_app_number] => 109632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109632 | Integrated circuit clock input buffer | Jul 1, 1998 | Issued |
Array
(
[id] => 3940190
[patent_doc_number] => 05953262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Output circuit of a semiconductor memory device for providing an intermediate potential to an output terminal'
[patent_app_type] => 1
[patent_app_number] => 9/109840
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6632
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/953/05953262.pdf
[firstpage_image] =>[orig_patent_app_number] => 109840
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109840 | Output circuit of a semiconductor memory device for providing an intermediate potential to an output terminal | Jul 1, 1998 | Issued |
Array
(
[id] => 4261935
[patent_doc_number] => RE037184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Semiconductor memory and screening test method thereof'
[patent_app_type] => 2
[patent_app_number] => 9/108266
[patent_app_country] => US
[patent_app_date] => 1998-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 33
[patent_no_of_words] => 14708
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037184.pdf
[firstpage_image] =>[orig_patent_app_number] => 108266
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/108266 | Semiconductor memory and screening test method thereof | Jun 30, 1998 | Issued |
Array
(
[id] => 4191861
[patent_doc_number] => 06038168
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor'
[patent_app_type] => 1
[patent_app_number] => 9/105339
[patent_app_country] => US
[patent_app_date] => 1998-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 1
[patent_no_of_words] => 2029
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038168.pdf
[firstpage_image] =>[orig_patent_app_number] => 105339
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105339 | Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor | Jun 25, 1998 | Issued |
Array
(
[id] => 3993689
[patent_doc_number] => 05949699
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 9/104041
[patent_app_country] => US
[patent_app_date] => 1998-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5137
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949699.pdf
[firstpage_image] =>[orig_patent_app_number] => 104041
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/104041 | Semiconductor integrated circuit device | Jun 24, 1998 | Issued |
Array
(
[id] => 3950483
[patent_doc_number] => 05930172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Page buffer for a multi-level flash memory with a limited number of latches per memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/103041
[patent_app_country] => US
[patent_app_date] => 1998-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3263
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930172.pdf
[firstpage_image] =>[orig_patent_app_number] => 103041
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/103041 | Page buffer for a multi-level flash memory with a limited number of latches per memory cell | Jun 22, 1998 | Issued |
Array
(
[id] => 3962295
[patent_doc_number] => 05999458
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Latch circuit, data output circuit and semiconductor device having the circuits'
[patent_app_type] => 1
[patent_app_number] => 9/100038
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 9
[patent_no_of_words] => 5068
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/999/05999458.pdf
[firstpage_image] =>[orig_patent_app_number] => 100038
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100038 | Latch circuit, data output circuit and semiconductor device having the circuits | Jun 18, 1998 | Issued |
Array
(
[id] => 3998568
[patent_doc_number] => 05959920
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Semiconductor memory device using sense amplifiers in a dummy cell area for increasing writing speed'
[patent_app_type] => 1
[patent_app_number] => 9/098339
[patent_app_country] => US
[patent_app_date] => 1998-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4496
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/959/05959920.pdf
[firstpage_image] =>[orig_patent_app_number] => 098339
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/098339 | Semiconductor memory device using sense amplifiers in a dummy cell area for increasing writing speed | Jun 16, 1998 | Issued |
Array
(
[id] => 3998220
[patent_doc_number] => 05959897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers'
[patent_app_type] => 1
[patent_app_number] => 9/098104
[patent_app_country] => US
[patent_app_date] => 1998-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10561
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/959/05959897.pdf
[firstpage_image] =>[orig_patent_app_number] => 098104
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/098104 | System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers | Jun 15, 1998 | Issued |
Array
(
[id] => 4048096
[patent_doc_number] => 05995434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Dynamic random access memory device having a self-refresh mode'
[patent_app_type] => 1
[patent_app_number] => 9/095931
[patent_app_country] => US
[patent_app_date] => 1998-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4761
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/995/05995434.pdf
[firstpage_image] =>[orig_patent_app_number] => 095931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095931 | Dynamic random access memory device having a self-refresh mode | Jun 11, 1998 | Issued |
Array
(
[id] => 3962245
[patent_doc_number] => 05956275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Memory-cell array and a method for repairing the same'
[patent_app_type] => 1
[patent_app_number] => 9/094439
[patent_app_country] => US
[patent_app_date] => 1998-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3464
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/956/05956275.pdf
[firstpage_image] =>[orig_patent_app_number] => 094439
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094439 | Memory-cell array and a method for repairing the same | Jun 8, 1998 | Issued |
Array
(
[id] => 4054494
[patent_doc_number] => 05909403
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Memory driving apparatus'
[patent_app_type] => 1
[patent_app_number] => 9/092950
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5736
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909403.pdf
[firstpage_image] =>[orig_patent_app_number] => 092950
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/092950 | Memory driving apparatus | Jun 7, 1998 | Issued |