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Array ( [id] => 3971010 [patent_doc_number] => 05901089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell' [patent_app_type] => 1 [patent_app_number] => 9/054370 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 21545 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901089.pdf [firstpage_image] =>[orig_patent_app_number] => 054370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970187 [patent_doc_number] => 05936898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Bit-line voltage limiting isolation circuit' [patent_app_type] => 1 [patent_app_number] => 9/053853 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5809 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936898.pdf [firstpage_image] =>[orig_patent_app_number] => 053853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896376 [patent_doc_number] => 05894441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Semiconductor memory device with redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 9/050354 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7786 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894441.pdf [firstpage_image] =>[orig_patent_app_number] => 050354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054509 [patent_doc_number] => 05909404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Refresh sampling built-in self test and repair circuit' [patent_app_type] => 1 [patent_app_number] => 9/049852 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8701 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909404.pdf [firstpage_image] =>[orig_patent_app_number] => 049852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970257 [patent_doc_number] => 05936902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method of testing for SRAM pull-down transistor sub-threshold leakage' [patent_app_type] => 1 [patent_app_number] => 9/048553 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1698 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936902.pdf [firstpage_image] =>[orig_patent_app_number] => 048553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359056 [patent_doc_number] => 06285608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for using supply voltage for testing in semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/045250 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2988 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285608.pdf [firstpage_image] =>[orig_patent_app_number] => 045250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359056 [patent_doc_number] => 06285608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for using supply voltage for testing in semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/045250 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2988 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285608.pdf [firstpage_image] =>[orig_patent_app_number] => 045250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359056 [patent_doc_number] => 06285608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for using supply voltage for testing in semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/045250 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2988 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285608.pdf [firstpage_image] =>[orig_patent_app_number] => 045250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4359056 [patent_doc_number] => 06285608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for using supply voltage for testing in semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/045250 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2988 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285608.pdf [firstpage_image] =>[orig_patent_app_number] => 045250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4234260 [patent_doc_number] => 06011740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Structure and method for providing additional configuration memories on an FPGA' [patent_app_type] => 1 [patent_app_number] => 9/035631 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2882 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011740.pdf [firstpage_image] =>[orig_patent_app_number] => 035631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4073301 [patent_doc_number] => 05896328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell' [patent_app_type] => 1 [patent_app_number] => 9/031556 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 10087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896328.pdf [firstpage_image] =>[orig_patent_app_number] => 031556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4005217 [patent_doc_number] => 05920508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/030250 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6615 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920508.pdf [firstpage_image] =>[orig_patent_app_number] => 030250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4230488 [patent_doc_number] => 06040993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for programming an analog/multi-level flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/028229 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4347 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040993.pdf [firstpage_image] =>[orig_patent_app_number] => 028229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937570 [patent_doc_number] => 05946268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal' [patent_app_type] => 1 [patent_app_number] => 9/012558 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8912 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946268.pdf [firstpage_image] =>[orig_patent_app_number] => 012558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915608 [patent_doc_number] => 05898641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Address transition circuit for a memory' [patent_app_type] => 1 [patent_app_number] => 9/012042 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2160 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898641.pdf [firstpage_image] =>[orig_patent_app_number] => 012042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960249 [patent_doc_number] => 05991199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Device and method for the programming of a memory' [patent_app_type] => 1 [patent_app_number] => 9/012938 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4929 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991199.pdf [firstpage_image] =>[orig_patent_app_number] => 012938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231364 [patent_doc_number] => 06088267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Nonvolatile semiconductor memory device having row decoder' [patent_app_type] => 1 [patent_app_number] => 9/006155 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088267.pdf [firstpage_image] =>[orig_patent_app_number] => 006155 [rel_patent_id] =>[rel_patent_doc_number] =>)