Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
09/000954 DATA-BIT REDUNDANCY IN SEMICONDUCTOR MEMORIES Dec 29, 1997 Issued
Array ( [id] => 4064738 [patent_doc_number] => 05969977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Electronic memory device having bit lines with block selector switches' [patent_app_type] => 1 [patent_app_number] => 8/998854 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5398 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969977.pdf [firstpage_image] =>[orig_patent_app_number] => 998854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998854
Electronic memory device having bit lines with block selector switches Dec 28, 1997 Issued
Array ( [id] => 3770514 [patent_doc_number] => 05852580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Repair fuse circuit in a flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/999350 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1223 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852580.pdf [firstpage_image] =>[orig_patent_app_number] => 999350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999350
Repair fuse circuit in a flash memory device Dec 28, 1997 Issued
Array ( [id] => 4045643 [patent_doc_number] => 05943258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Memory with storage cells having SOI drive and access transistors with tied floating body connections' [patent_app_type] => 1 [patent_app_number] => 8/998153 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 9448 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943258.pdf [firstpage_image] =>[orig_patent_app_number] => 998153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998153
Memory with storage cells having SOI drive and access transistors with tied floating body connections Dec 23, 1997 Issued
Array ( [id] => 3993760 [patent_doc_number] => 05949703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor memory device in which data in programmable ROM can be apparently rewritten' [patent_app_type] => 1 [patent_app_number] => 8/996752 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 49 [patent_no_of_words] => 18946 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949703.pdf [firstpage_image] =>[orig_patent_app_number] => 996752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996752
Semiconductor memory device in which data in programmable ROM can be apparently rewritten Dec 22, 1997 Issued
Array ( [id] => 3937080 [patent_doc_number] => 05946234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Constant current source programming of electrically programmable memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/993555 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2862 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946234.pdf [firstpage_image] =>[orig_patent_app_number] => 993555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993555
Constant current source programming of electrically programmable memory arrays Dec 17, 1997 Issued
Array ( [id] => 4054273 [patent_doc_number] => 05909390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values' [patent_app_type] => 1 [patent_app_number] => 8/991650 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5914 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909390.pdf [firstpage_image] =>[orig_patent_app_number] => 991650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991650
Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values Dec 15, 1997 Issued
Array ( [id] => 4025960 [patent_doc_number] => 05963487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Write enabling circuitry for a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/991231 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2490 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963487.pdf [firstpage_image] =>[orig_patent_app_number] => 991231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991231
Write enabling circuitry for a semiconductor memory Dec 15, 1997 Issued
Array ( [id] => 4395195 [patent_doc_number] => 06278632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and circuitry for performing analog over-program and under-program detection for a multistate memory cell' [patent_app_type] => 1 [patent_app_number] => 8/991216 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7158 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278632.pdf [firstpage_image] =>[orig_patent_app_number] => 991216 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991216
Method and circuitry for performing analog over-program and under-program detection for a multistate memory cell Dec 11, 1997 Issued
Array ( [id] => 3971371 [patent_doc_number] => 05901110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Synchronous memory with dual sensing output path each of which is connected to latch circuit' [patent_app_type] => 1 [patent_app_number] => 8/988451 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1888 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901110.pdf [firstpage_image] =>[orig_patent_app_number] => 988451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988451
Synchronous memory with dual sensing output path each of which is connected to latch circuit Dec 9, 1997 Issued
Array ( [id] => 1589964 [patent_doc_number] => 06359809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Oscillator for simultaneously generating multiple clock signals of different frequencies' [patent_app_type] => B1 [patent_app_number] => 08/988225 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5961 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359809.pdf [firstpage_image] =>[orig_patent_app_number] => 08988225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988225
Oscillator for simultaneously generating multiple clock signals of different frequencies Dec 9, 1997 Issued
Array ( [id] => 4010543 [patent_doc_number] => 05923588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Non-volatile semiconductor memory device with a plurality of programming voltage levels' [patent_app_type] => 1 [patent_app_number] => 8/986310 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 24193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923588.pdf [firstpage_image] =>[orig_patent_app_number] => 986310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986310
Non-volatile semiconductor memory device with a plurality of programming voltage levels Dec 4, 1997 Issued
Array ( [id] => 4027451 [patent_doc_number] => 05881018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Device and method for automatically setting status of dynamic random access memory through control of clock enable signal' [patent_app_type] => 1 [patent_app_number] => 8/980454 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3544 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881018.pdf [firstpage_image] =>[orig_patent_app_number] => 980454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980454
Device and method for automatically setting status of dynamic random access memory through control of clock enable signal Nov 27, 1997 Issued
Array ( [id] => 3792203 [patent_doc_number] => 05818770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Circuit and method for write recovery control' [patent_app_type] => 1 [patent_app_number] => 8/979302 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2136 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818770.pdf [firstpage_image] =>[orig_patent_app_number] => 979302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979302
Circuit and method for write recovery control Nov 25, 1997 Issued
Array ( [id] => 4015137 [patent_doc_number] => 05859799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels' [patent_app_type] => 1 [patent_app_number] => 8/975151 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 16560 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859799.pdf [firstpage_image] =>[orig_patent_app_number] => 975151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975151
Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels Nov 19, 1997 Issued
Array ( [id] => 4073414 [patent_doc_number] => 05896336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Device and method for driving a conductive path with a signal' [patent_app_type] => 1 [patent_app_number] => 8/974747 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 12980 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896336.pdf [firstpage_image] =>[orig_patent_app_number] => 974747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974747
Device and method for driving a conductive path with a signal Nov 18, 1997 Issued
Array ( [id] => 3906794 [patent_doc_number] => RE036404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Semiconductor memory device for use in apparatus requiring high-speed access to memory cells' [patent_app_type] => 2 [patent_app_number] => 8/970780 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036404.pdf [firstpage_image] =>[orig_patent_app_number] => 970780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970780
Semiconductor memory device for use in apparatus requiring high-speed access to memory cells Nov 13, 1997 Issued
Array ( [id] => 4005211 [patent_doc_number] => 05892728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Column decoder configuration for a 1T/1C ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/970454 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 53 [patent_no_of_words] => 19377 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892728.pdf [firstpage_image] =>[orig_patent_app_number] => 970454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970454
Column decoder configuration for a 1T/1C ferroelectric memory Nov 13, 1997 Issued
Array ( [id] => 4026979 [patent_doc_number] => 05880989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Sensing methodology for a 1T/1C ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/970453 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 53 [patent_no_of_words] => 19194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880989.pdf [firstpage_image] =>[orig_patent_app_number] => 970453 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970453
Sensing methodology for a 1T/1C ferroelectric memory Nov 13, 1997 Issued
Array ( [id] => 3962118 [patent_doc_number] => 05956266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Reference cell for a 1T/1C ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/970452 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 53 [patent_no_of_words] => 19381 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956266.pdf [firstpage_image] =>[orig_patent_app_number] => 970452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970452
Reference cell for a 1T/1C ferroelectric memory Nov 13, 1997 Issued
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