Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3915207 [patent_doc_number] => 05898616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Semiconductor nonvolatile memory and source circuit for this memory' [patent_app_type] => 1 [patent_app_number] => 8/970500 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9211 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898616.pdf [firstpage_image] =>[orig_patent_app_number] => 970500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970500
Semiconductor nonvolatile memory and source circuit for this memory Nov 13, 1997 Issued
Array ( [id] => 4005085 [patent_doc_number] => 05920499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method of decoding a diode type read only memory' [patent_app_type] => 1 [patent_app_number] => 8/969151 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1653 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920499.pdf [firstpage_image] =>[orig_patent_app_number] => 969151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969151
Method of decoding a diode type read only memory Nov 11, 1997 Issued
Array ( [id] => 4015282 [patent_doc_number] => 05859809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Semiconductor device of daisy chain structure having independent refresh apparatus' [patent_app_type] => 1 [patent_app_number] => 8/966355 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2107 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859809.pdf [firstpage_image] =>[orig_patent_app_number] => 966355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966355
Semiconductor device of daisy chain structure having independent refresh apparatus Nov 6, 1997 Issued
Array ( [id] => 4193806 [patent_doc_number] => 06021065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Spin dependent tunneling memory' [patent_app_type] => 1 [patent_app_number] => 8/965333 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 19609 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021065.pdf [firstpage_image] =>[orig_patent_app_number] => 965333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965333
Spin dependent tunneling memory Nov 5, 1997 Issued
Array ( [id] => 3980536 [patent_doc_number] => 05886924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Nonvolatile semiconductor memory having sub-arrays formed within pocket wells' [patent_app_type] => 1 [patent_app_number] => 8/965054 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886924.pdf [firstpage_image] =>[orig_patent_app_number] => 965054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965054
Nonvolatile semiconductor memory having sub-arrays formed within pocket wells Nov 4, 1997 Issued
Array ( [id] => 4073259 [patent_doc_number] => 05896325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'IC card with error processing unit for sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 8/962839 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6893 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896325.pdf [firstpage_image] =>[orig_patent_app_number] => 962839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962839
IC card with error processing unit for sense amplifiers Nov 2, 1997 Issued
Array ( [id] => 3816141 [patent_doc_number] => 05854771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Semiconductor memory device including copy circuit' [patent_app_type] => 1 [patent_app_number] => 8/963355 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3893 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854771.pdf [firstpage_image] =>[orig_patent_app_number] => 963355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963355
Semiconductor memory device including copy circuit Nov 2, 1997 Issued
Array ( [id] => 3950388 [patent_doc_number] => 05930165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Fringe field superconducting system' [patent_app_type] => 1 [patent_app_number] => 8/962454 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6635 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930165.pdf [firstpage_image] =>[orig_patent_app_number] => 962454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962454
Fringe field superconducting system Oct 30, 1997 Issued
Array ( [id] => 3994037 [patent_doc_number] => 05862095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system' [patent_app_type] => 1 [patent_app_number] => 8/962351 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11810 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862095.pdf [firstpage_image] =>[orig_patent_app_number] => 962351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962351
Semiconductor memory having both a refresh operation cycle and a normal operation cycle and employing an address non-multiplex system Oct 30, 1997 Issued
Array ( [id] => 3889517 [patent_doc_number] => 05825698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Redundancy decoding circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/961052 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2442 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825698.pdf [firstpage_image] =>[orig_patent_app_number] => 961052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961052
Redundancy decoding circuit for a semiconductor memory device Oct 29, 1997 Issued
Array ( [id] => 3960532 [patent_doc_number] => 05991217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Fast SRAM design using embedded sense amps' [patent_app_type] => 1 [patent_app_number] => 8/967194 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1281 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991217.pdf [firstpage_image] =>[orig_patent_app_number] => 967194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967194
Fast SRAM design using embedded sense amps Oct 28, 1997 Issued
Array ( [id] => 4027186 [patent_doc_number] => 05907508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell' [patent_app_type] => 1 [patent_app_number] => 8/959652 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5282 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907508.pdf [firstpage_image] =>[orig_patent_app_number] => 959652 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959652
Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell Oct 27, 1997 Issued
Array ( [id] => 4061317 [patent_doc_number] => 05870349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Data processing system and method for generating memory control signals with clock skew tolerance' [patent_app_type] => 1 [patent_app_number] => 8/959653 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870349.pdf [firstpage_image] =>[orig_patent_app_number] => 959653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959653
Data processing system and method for generating memory control signals with clock skew tolerance Oct 27, 1997 Issued
Array ( [id] => 3950685 [patent_doc_number] => 05930186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and apparatus for testing counter and serial access memory' [patent_app_type] => 1 [patent_app_number] => 8/959443 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3250 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930186.pdf [firstpage_image] =>[orig_patent_app_number] => 959443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959443
Method and apparatus for testing counter and serial access memory Oct 27, 1997 Issued
Array ( [id] => 4077441 [patent_doc_number] => 05867421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Integrated circuit memory device having reduced stress across large on-chip capacitor' [patent_app_type] => 1 [patent_app_number] => 8/958942 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2420 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867421.pdf [firstpage_image] =>[orig_patent_app_number] => 958942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958942
Integrated circuit memory device having reduced stress across large on-chip capacitor Oct 27, 1997 Issued
Array ( [id] => 3883123 [patent_doc_number] => 05838632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => 1 [patent_app_number] => 8/956355 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1583 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838632.pdf [firstpage_image] =>[orig_patent_app_number] => 956355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956355
Semiconductor memory apparatus Oct 22, 1997 Issued
Array ( [id] => 3873256 [patent_doc_number] => 05796655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Memory cell having programmed margin verification' [patent_app_type] => 1 [patent_app_number] => 8/954152 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4079 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796655.pdf [firstpage_image] =>[orig_patent_app_number] => 954152 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954152
Memory cell having programmed margin verification Oct 19, 1997 Issued
Array ( [id] => 3998666 [patent_doc_number] => 05959927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Semiconductor integrated circuit device having hierarchical power source arrangement' [patent_app_type] => 1 [patent_app_number] => 8/953728 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 68 [patent_no_of_words] => 48751 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959927.pdf [firstpage_image] =>[orig_patent_app_number] => 953728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953728
Semiconductor integrated circuit device having hierarchical power source arrangement Oct 16, 1997 Issued
Array ( [id] => 3998339 [patent_doc_number] => 05959904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Dynamic column redundancy driving circuit for synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/953351 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2754 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959904.pdf [firstpage_image] =>[orig_patent_app_number] => 953351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953351
Dynamic column redundancy driving circuit for synchronous semiconductor memory device Oct 16, 1997 Issued
Array ( [id] => 4131329 [patent_doc_number] => 06072733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Programmable sense amplifier delay (PSAD) circuit which is matched to the memory array' [patent_app_type] => 1 [patent_app_number] => 8/953690 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2624 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072733.pdf [firstpage_image] =>[orig_patent_app_number] => 953690 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953690
Programmable sense amplifier delay (PSAD) circuit which is matched to the memory array Oct 16, 1997 Issued
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