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Vu Anh Le

Examiner (ID: 5941, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2824, 0, 2825, 2511, 2818
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17085237 [patent_doc_number] => 20210280244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/809453 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809453
Modified write voltage for memory devices Mar 3, 2020 Issued
Array ( [id] => 16585840 [patent_doc_number] => 20210020242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => NONVOLATILE MEMORY APPARATUS FOR MITIGATING DISTURBANCES AND AN OPERATING METHOD OF THE NONVOLATILE MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/803658 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803658 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803658
Nonvolatile memory apparatus for mitigating disturbances and an operating method of the nonvolatile memory apparatus Feb 26, 2020 Issued
Array ( [id] => 16789001 [patent_doc_number] => 10991438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Method and memory used for reducing program disturbance by adjusting voltage of dummy word line [patent_app_type] => utility [patent_app_number] => 16/799806 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799806
Method and memory used for reducing program disturbance by adjusting voltage of dummy word line Feb 23, 2020 Issued
Array ( [id] => 16479331 [patent_doc_number] => 10854284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Computational memory cell and processing array device with ratioless write port [patent_app_type] => utility [patent_app_number] => 16/785141 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6253 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785141
Computational memory cell and processing array device with ratioless write port Feb 6, 2020 Issued
Array ( [id] => 16684159 [patent_doc_number] => 10943648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Ultra low VDD memory cell with ratioless write port [patent_app_type] => utility [patent_app_number] => 16/785153 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6253 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785153
Ultra low VDD memory cell with ratioless write port Feb 6, 2020 Issued
Array ( [id] => 16738694 [patent_doc_number] => 10964355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Memory device with strap cells [patent_app_type] => utility [patent_app_number] => 16/744076 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744076
Memory device with strap cells Jan 14, 2020 Issued
Array ( [id] => 15841509 [patent_doc_number] => 20200136037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/726513 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726513
Variable resistance memory device and method of manufacturing the same Dec 23, 2019 Issued
Array ( [id] => 16097971 [patent_doc_number] => 20200202972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => ELECTRONIC CHIP MEMORY [patent_app_type] => utility [patent_app_number] => 16/709019 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709019
Electronic chip memory Dec 9, 2019 Issued
Array ( [id] => 16738695 [patent_doc_number] => 10964356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Compute-in-memory bit cell [patent_app_type] => utility [patent_app_number] => 16/706429 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7725 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706429
Compute-in-memory bit cell Dec 5, 2019 Issued
Array ( [id] => 17047803 [patent_doc_number] => 11100993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => TCAM architecture where content-based search is conductible [patent_app_type] => utility [patent_app_number] => 16/703319 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3935 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703319 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703319
TCAM architecture where content-based search is conductible Dec 3, 2019 Issued
Array ( [id] => 17318541 [patent_doc_number] => 20210407591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Systems and Methods for Stabilizing Cell Threshold Voltage [patent_app_type] => utility [patent_app_number] => 16/760420 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16760420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/760420
Systems and methods for stabilizing cell threshold voltage Dec 2, 2019 Issued
Array ( [id] => 15717121 [patent_doc_number] => 20200105328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/701006 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701006
Access line management for an array of memory cells Dec 1, 2019 Issued
Array ( [id] => 15687501 [patent_doc_number] => 20200098414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => ACCESS LINE MANAGEMENT FOR AN ARRAY OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/695848 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695848
Access line management for an array of memory cells Nov 25, 2019 Issued
Array ( [id] => 15688641 [patent_doc_number] => 20200098984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/694844 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694844
Electronic device and method for fabricating the same Nov 24, 2019 Issued
Array ( [id] => 16080131 [patent_doc_number] => 20200194052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device [patent_app_type] => utility [patent_app_number] => 16/692043 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692043
Memory system topologies including a buffer device and an integrated circuit memory device Nov 21, 2019 Issued
Array ( [id] => 15937053 [patent_doc_number] => 20200160160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => ARTIFICIAL NEURAL NETWORK CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/687599 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687599
Artificial neural network circuit Nov 17, 2019 Issued
Array ( [id] => 17862015 [patent_doc_number] => 11443174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Machine learning accelerator [patent_app_type] => utility [patent_app_number] => 16/682466 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6577 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682466
Machine learning accelerator Nov 12, 2019 Issued
Array ( [id] => 16417594 [patent_doc_number] => 10825494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => DFE conditioning for write operations of a memory device [patent_app_type] => utility [patent_app_number] => 16/683018 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 11950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683018
DFE conditioning for write operations of a memory device Nov 12, 2019 Issued
Array ( [id] => 17380907 [patent_doc_number] => 11238928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Read-write circuit and read-write method of memristor [patent_app_type] => utility [patent_app_number] => 17/049024 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6036 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17049024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/049024
Read-write circuit and read-write method of memristor Nov 11, 2019 Issued
Array ( [id] => 16896047 [patent_doc_number] => 11037608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Stacked memory device and memory system including the same [patent_app_type] => utility [patent_app_number] => 16/677289 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677289 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677289
Stacked memory device and memory system including the same Nov 6, 2019 Issued
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