Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3889328 [patent_doc_number] => 05825686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Multi-value read-only memory cell having an improved signal-to-noise ratio' [patent_app_type] => 1 [patent_app_number] => 8/875955 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3387 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825686.pdf [firstpage_image] =>[orig_patent_app_number] => 875955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/875955
Multi-value read-only memory cell having an improved signal-to-noise ratio Aug 10, 1997 Issued
Array ( [id] => 3802227 [patent_doc_number] => 05841690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/908587 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 14881 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841690.pdf [firstpage_image] =>[orig_patent_app_number] => 908587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908587
Semiconductor memory Aug 7, 1997 Issued
Array ( [id] => 3756829 [patent_doc_number] => 05802001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Burn-in checking apparatus for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/905955 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 1476 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802001.pdf [firstpage_image] =>[orig_patent_app_number] => 905955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905955
Burn-in checking apparatus for semiconductor memory device Aug 4, 1997 Issued
Array ( [id] => 4046055 [patent_doc_number] => 05943285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Arrangement of memory blocks and pads' [patent_app_type] => 1 [patent_app_number] => 8/904955 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 47 [patent_no_of_words] => 19116 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943285.pdf [firstpage_image] =>[orig_patent_app_number] => 904955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904955
Arrangement of memory blocks and pads Jul 31, 1997 Issued
Array ( [id] => 3998322 [patent_doc_number] => 05959903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Column redundancy in semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/904153 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959903.pdf [firstpage_image] =>[orig_patent_app_number] => 904153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904153
Column redundancy in semiconductor memories Jul 30, 1997 Issued
Array ( [id] => 3853687 [patent_doc_number] => 05848007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Redundancy circuit for semiconductor storage apparatus' [patent_app_type] => 1 [patent_app_number] => 8/901952 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9732 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848007.pdf [firstpage_image] =>[orig_patent_app_number] => 901952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901952
Redundancy circuit for semiconductor storage apparatus Jul 28, 1997 Issued
Array ( [id] => 3797901 [patent_doc_number] => 05822241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'DRAM pass transistors' [patent_app_type] => 1 [patent_app_number] => 8/901853 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3037 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822241.pdf [firstpage_image] =>[orig_patent_app_number] => 901853 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901853
DRAM pass transistors Jul 28, 1997 Issued
Array ( [id] => 4047964 [patent_doc_number] => 05995425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Design of provably correct storage arrays' [patent_app_type] => 1 [patent_app_number] => 8/898826 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5693 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995425.pdf [firstpage_image] =>[orig_patent_app_number] => 898826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/898826
Design of provably correct storage arrays Jul 22, 1997 Issued
Array ( [id] => 3866979 [patent_doc_number] => 05768198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Semiconductor memory having redundancy function in block write operation' [patent_app_type] => 1 [patent_app_number] => 8/892029 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3013 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768198.pdf [firstpage_image] =>[orig_patent_app_number] => 892029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892029
Semiconductor memory having redundancy function in block write operation Jul 13, 1997 Issued
Array ( [id] => 3892198 [patent_doc_number] => 05805509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method and structure for generating a boosted word line voltage and back bias voltage for a memory array' [patent_app_type] => 1 [patent_app_number] => 8/891124 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5301 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805509.pdf [firstpage_image] =>[orig_patent_app_number] => 891124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891124
Method and structure for generating a boosted word line voltage and back bias voltage for a memory array Jul 9, 1997 Issued
Array ( [id] => 3774908 [patent_doc_number] => 05844844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'FPGA memory element programmably triggered on both clock edges' [patent_app_type] => 1 [patent_app_number] => 8/890951 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5388 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844844.pdf [firstpage_image] =>[orig_patent_app_number] => 890951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890951
FPGA memory element programmably triggered on both clock edges Jul 8, 1997 Issued
Array ( [id] => 3940517 [patent_doc_number] => 05953284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same' [patent_app_type] => 1 [patent_app_number] => 8/890055 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15241 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953284.pdf [firstpage_image] =>[orig_patent_app_number] => 890055 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890055
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same Jul 8, 1997 Issued
Array ( [id] => 3882914 [patent_doc_number] => 05838617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method for changing electrically programmable read-only memory devices' [patent_app_type] => 1 [patent_app_number] => 8/888030 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6880 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838617.pdf [firstpage_image] =>[orig_patent_app_number] => 888030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888030
Method for changing electrically programmable read-only memory devices Jul 2, 1997 Issued
Array ( [id] => 3821402 [patent_doc_number] => 05831917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Techniques for reducing redundant element fuses in a dynamic random access memory array' [patent_app_type] => 1 [patent_app_number] => 8/884854 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8155 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831917.pdf [firstpage_image] =>[orig_patent_app_number] => 884854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884854
Techniques for reducing redundant element fuses in a dynamic random access memory array Jun 29, 1997 Issued
Array ( [id] => 4011991 [patent_doc_number] => 05986932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Non-volatile static random access memory and methods for using same' [patent_app_type] => 1 [patent_app_number] => 8/885156 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6531 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986932.pdf [firstpage_image] =>[orig_patent_app_number] => 885156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885156
Non-volatile static random access memory and methods for using same Jun 29, 1997 Issued
Array ( [id] => 4054632 [patent_doc_number] => 05875138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Dynamic access memory equalizer circuits and methods therefor' [patent_app_type] => 1 [patent_app_number] => 8/884855 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4773 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875138.pdf [firstpage_image] =>[orig_patent_app_number] => 884855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884855
Dynamic access memory equalizer circuits and methods therefor Jun 29, 1997 Issued
Array ( [id] => 3905100 [patent_doc_number] => 05835420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Node-precise voltage regulation for a MOS memory system' [patent_app_type] => 1 [patent_app_number] => 8/884251 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 17580 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835420.pdf [firstpage_image] =>[orig_patent_app_number] => 884251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884251
Node-precise voltage regulation for a MOS memory system Jun 26, 1997 Issued
Array ( [id] => 4147873 [patent_doc_number] => 06122202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'CASB buffer circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/881954 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3444 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122202.pdf [firstpage_image] =>[orig_patent_app_number] => 881954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881954
CASB buffer circuit of semiconductor memory device Jun 24, 1997 Issued
Array ( [id] => 3821389 [patent_doc_number] => 05831916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Redundant circuits and methods therefor' [patent_app_type] => 1 [patent_app_number] => 8/879726 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831916.pdf [firstpage_image] =>[orig_patent_app_number] => 879726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879726
Redundant circuits and methods therefor Jun 19, 1997 Issued
Array ( [id] => 4061198 [patent_doc_number] => 05870341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Memory column redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 8/878755 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6136 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870341.pdf [firstpage_image] =>[orig_patent_app_number] => 878755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878755
Memory column redundancy circuit Jun 18, 1997 Issued
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