Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3950653 [patent_doc_number] => 05930184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Memory device having two or more memory arrays and a testpath connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath' [patent_app_type] => 1 [patent_app_number] => 8/878752 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5198 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930184.pdf [firstpage_image] =>[orig_patent_app_number] => 878752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878752
Memory device having two or more memory arrays and a testpath connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath Jun 18, 1997 Issued
Array ( [id] => 4038533 [patent_doc_number] => 05903498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Low-supply-voltage nonvolatile memory device with voltage boosting' [patent_app_type] => 1 [patent_app_number] => 8/877927 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4519 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903498.pdf [firstpage_image] =>[orig_patent_app_number] => 877927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877927
Low-supply-voltage nonvolatile memory device with voltage boosting Jun 17, 1997 Issued
Array ( [id] => 3790278 [patent_doc_number] => 05757717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor circuit having circuit supplying voltage higher than power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/877553 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5637 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757717.pdf [firstpage_image] =>[orig_patent_app_number] => 877553 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877553
Semiconductor circuit having circuit supplying voltage higher than power supply voltage Jun 16, 1997 Issued
Array ( [id] => 3962433 [patent_doc_number] => 05956289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Clock signal from an adjustable oscillator for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/877253 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9941 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956289.pdf [firstpage_image] =>[orig_patent_app_number] => 877253 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877253
Clock signal from an adjustable oscillator for an integrated circuit Jun 16, 1997 Issued
Array ( [id] => 3889356 [patent_doc_number] => 05825688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Non-volatile semiconductor storage apparatus' [patent_app_type] => 1 [patent_app_number] => 8/876709 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7114 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825688.pdf [firstpage_image] =>[orig_patent_app_number] => 876709 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876709
Non-volatile semiconductor storage apparatus Jun 15, 1997 Issued
Array ( [id] => 3783907 [patent_doc_number] => 05774403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'PVT self aligning internal delay line and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/873854 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4062 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774403.pdf [firstpage_image] =>[orig_patent_app_number] => 873854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873854
PVT self aligning internal delay line and method of operation Jun 11, 1997 Issued
Array ( [id] => 3789911 [patent_doc_number] => 05757691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor memory device having wiring for selection of redundant cells but without useless region on chip' [patent_app_type] => 1 [patent_app_number] => 8/869637 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4036 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757691.pdf [firstpage_image] =>[orig_patent_app_number] => 869637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869637
Semiconductor memory device having wiring for selection of redundant cells but without useless region on chip Jun 4, 1997 Issued
Array ( [id] => 3790018 [patent_doc_number] => 05757699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Programming which can make threshold voltages of programmed memory cells have a narrow distribution in a nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/862965 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6072 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757699.pdf [firstpage_image] =>[orig_patent_app_number] => 862965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862965
Programming which can make threshold voltages of programmed memory cells have a narrow distribution in a nonvolatile semiconductor memory Jun 2, 1997 Issued
Array ( [id] => 3802789 [patent_doc_number] => 05841727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/867855 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4542 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841727.pdf [firstpage_image] =>[orig_patent_app_number] => 867855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867855
Semiconductor memory device Jun 2, 1997 Issued
Array ( [id] => 3807941 [patent_doc_number] => 05781489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 8/866270 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5550 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781489.pdf [firstpage_image] =>[orig_patent_app_number] => 866270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866270
Semiconductor storage device May 29, 1997 Issued
Array ( [id] => 3792542 [patent_doc_number] => 05818788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation' [patent_app_type] => 1 [patent_app_number] => 8/865968 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4746 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818788.pdf [firstpage_image] =>[orig_patent_app_number] => 865968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865968
Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation May 29, 1997 Issued
Array ( [id] => 4037156 [patent_doc_number] => 05883844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof' [patent_app_type] => 1 [patent_app_number] => 8/862969 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4152 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883844.pdf [firstpage_image] =>[orig_patent_app_number] => 862969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862969
Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof May 22, 1997 Issued
Array ( [id] => 3809157 [patent_doc_number] => 05828598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'MRAM with high GMR ratio' [patent_app_type] => 1 [patent_app_number] => 8/862738 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4508 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828598.pdf [firstpage_image] =>[orig_patent_app_number] => 862738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862738
MRAM with high GMR ratio May 22, 1997 Issued
Array ( [id] => 3915182 [patent_doc_number] => 05898614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/861033 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 11094 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898614.pdf [firstpage_image] =>[orig_patent_app_number] => 861033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861033
Non-volatile semiconductor memory device May 20, 1997 Issued
Array ( [id] => 3873202 [patent_doc_number] => 05796650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Memory circuit including write control unit wherein subthreshold leakage may be reduced' [patent_app_type] => 1 [patent_app_number] => 8/858270 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796650.pdf [firstpage_image] =>[orig_patent_app_number] => 858270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858270
Memory circuit including write control unit wherein subthreshold leakage may be reduced May 18, 1997 Issued
Array ( [id] => 3753357 [patent_doc_number] => 05754481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Clock synchronous type DRAM with latch' [patent_app_type] => 1 [patent_app_number] => 8/857559 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8315 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754481.pdf [firstpage_image] =>[orig_patent_app_number] => 857559 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857559
Clock synchronous type DRAM with latch May 15, 1997 Issued
Array ( [id] => 3866651 [patent_doc_number] => 05768177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Controlled delay circuit for use in synchronized semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/855535 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5282 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768177.pdf [firstpage_image] =>[orig_patent_app_number] => 855535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855535
Controlled delay circuit for use in synchronized semiconductor memory May 12, 1997 Issued
Array ( [id] => 3939912 [patent_doc_number] => 05877993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Memory circuit voltage regulator' [patent_app_type] => 1 [patent_app_number] => 8/855555 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7212 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877993.pdf [firstpage_image] =>[orig_patent_app_number] => 855555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855555
Memory circuit voltage regulator May 12, 1997 Issued
Array ( [id] => 3993987 [patent_doc_number] => 05862092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Read bitline writer for fallthru in fifos' [patent_app_type] => 1 [patent_app_number] => 8/852837 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862092.pdf [firstpage_image] =>[orig_patent_app_number] => 852837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852837
Read bitline writer for fallthru in fifos May 6, 1997 Issued
Array ( [id] => 4073143 [patent_doc_number] => 05896317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Nonvolatile semiconductor memory device having data line dedicated to data loading' [patent_app_type] => 1 [patent_app_number] => 8/852353 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6794 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896317.pdf [firstpage_image] =>[orig_patent_app_number] => 852353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852353
Nonvolatile semiconductor memory device having data line dedicated to data loading May 6, 1997 Issued
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