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Array ( [id] => 3853496 [patent_doc_number] => 05847995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Nonvolatile semiconductor memory device having a plurality of blocks provided on a plurality of electrically isolated wells' [patent_app_type] => 1 [patent_app_number] => 8/852354 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 12619 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847995.pdf [firstpage_image] =>[orig_patent_app_number] => 852354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015111 [patent_doc_number] => 05859797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Biasing circuit for UPROM cells with low voltage supply' [patent_app_type] => 1 [patent_app_number] => 8/846753 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3497 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859797.pdf [firstpage_image] =>[orig_patent_app_number] => 846753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3798139 [patent_doc_number] => 05822259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'UPROM cell for low voltage supply' [patent_app_type] => 1 [patent_app_number] => 8/846755 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3020 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822259.pdf [firstpage_image] =>[orig_patent_app_number] => 846755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915054 [patent_doc_number] => 05898606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 8/841372 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 124 [patent_figures_cnt] => 159 [patent_no_of_words] => 43516 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898606.pdf [firstpage_image] =>[orig_patent_app_number] => 841372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3792233 [patent_doc_number] => 05818772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Semiconductor memory devices having a built-in test function' [patent_app_type] => 1 [patent_app_number] => 8/841368 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7409 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818772.pdf [firstpage_image] =>[orig_patent_app_number] => 841368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3798208 [patent_doc_number] => 05822264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Dynamic semiconductor memory device with SOI structure and body refresh circuitry' [patent_app_type] => 1 [patent_app_number] => 8/837167 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 44 [patent_no_of_words] => 24822 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822264.pdf [firstpage_image] =>[orig_patent_app_number] => 837167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3905155 [patent_doc_number] => 05835424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/833754 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 42 [patent_no_of_words] => 7453 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835424.pdf [firstpage_image] =>[orig_patent_app_number] => 833754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3866706 [patent_doc_number] => 05768181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Magnetic device having multi-layer with insulating and conductive layers' [patent_app_type] => 1 [patent_app_number] => 8/834968 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768181.pdf [firstpage_image] =>[orig_patent_app_number] => 834968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3809407 [patent_doc_number] => 05828614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Memory cell sensing method and circuitry for bit line equalization' [patent_app_type] => 1 [patent_app_number] => 8/834942 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828614.pdf [firstpage_image] =>[orig_patent_app_number] => 834942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4034416 [patent_doc_number] => 05926414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'High-efficiency miniature magnetic integrated circuit structures' [patent_app_type] => 1 [patent_app_number] => 8/833151 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 8859 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926414.pdf [firstpage_image] =>[orig_patent_app_number] => 833151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824978 [patent_doc_number] => 05812462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Integrated circuit clock input buffer' [patent_app_type] => 1 [patent_app_number] => 8/832437 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2994 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812462.pdf [firstpage_image] =>[orig_patent_app_number] => 832437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3809143 [patent_doc_number] => 05828597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Low voltage, low power static random access memory cell' [patent_app_type] => 1 [patent_app_number] => 8/831811 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2782 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828597.pdf [firstpage_image] =>[orig_patent_app_number] => 831811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824662 [patent_doc_number] => 05812445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Low voltage, low power operable static random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/825063 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 58 [patent_no_of_words] => 30516 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812445.pdf [firstpage_image] =>[orig_patent_app_number] => 825063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3904808 [patent_doc_number] => 05835402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Non-volatile storage for standard CMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/825236 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 7616 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835402.pdf [firstpage_image] =>[orig_patent_app_number] => 825236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892036 [patent_doc_number] => 05805497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Semiconductor static random access memory cell with additional capacitor coupled to memory nodes and process of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/827367 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 8794 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 631 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805497.pdf [firstpage_image] =>[orig_patent_app_number] => 827367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845564 [patent_doc_number] => 05815440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor memory device with electrically controllable threshold voltage' [patent_app_type] => 1 [patent_app_number] => 8/822036 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 104 [patent_no_of_words] => 28275 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815440.pdf [firstpage_image] =>[orig_patent_app_number] => 822036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3839201 [patent_doc_number] => 05815023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Unbalanced multiplexer and arbiter combination' [patent_app_type] => 1 [patent_app_number] => 8/821266 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815023.pdf [firstpage_image] =>[orig_patent_app_number] => 821266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055698 [patent_doc_number] => 05869978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Circuit for removing noise components of oscillator' [patent_app_type] => 1 [patent_app_number] => 8/822090 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 34 [patent_no_of_words] => 6961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869978.pdf [firstpage_image] =>[orig_patent_app_number] => 822090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3804619 [patent_doc_number] => 05726946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Semiconductor integrated circuit device having hierarchical power source arrangement' [patent_app_type] => 1 [patent_app_number] => 8/820545 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 68 [patent_no_of_words] => 48753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726946.pdf [firstpage_image] =>[orig_patent_app_number] => 820545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3809070 [patent_doc_number] => 05828592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Analog signal recording and playback integrated circuit and message management system' [patent_app_type] => 1 [patent_app_number] => 8/819665 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7797 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828592.pdf [firstpage_image] =>[orig_patent_app_number] => 819665 [rel_patent_id] =>[rel_patent_doc_number] =>)