Vu Anh Le

Array ( [id] => 3873307 [patent_doc_number] => 05796660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Memory device and serial-parallel data transform circuit' [patent_app_type] => 1 [patent_app_number] => 8/815417 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5428 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796660.pdf [firstpage_image] =>[orig_patent_app_number] => 815417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3792420 [patent_doc_number] => 05818782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/814507 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 38 [patent_no_of_words] => 11075 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818782.pdf [firstpage_image] =>[orig_patent_app_number] => 814507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4060950 [patent_doc_number] => 05870324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Contents-addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/750765 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5055 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870324.pdf [firstpage_image] =>[orig_patent_app_number] => 750765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884950 [patent_doc_number] => 05805016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Variable capacitor based on frequency of operation' [patent_app_type] => 1 [patent_app_number] => 8/812632 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3542 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805016.pdf [firstpage_image] =>[orig_patent_app_number] => 812632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867161 [patent_doc_number] => 05793240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method and circuit for thermal asperity compensation in a data channel' [patent_app_type] => 1 [patent_app_number] => 8/812678 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2515 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793240.pdf [firstpage_image] =>[orig_patent_app_number] => 812678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752082 [patent_doc_number] => 05787039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Low current floating gate programming with bit-by-bit verification' [patent_app_type] => 1 [patent_app_number] => 8/812615 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8393 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787039.pdf [firstpage_image] =>[orig_patent_app_number] => 812615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892447 [patent_doc_number] => 05748539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Recursive multi-channel interface' [patent_app_type] => 1 [patent_app_number] => 8/811909 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6139 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748539.pdf [firstpage_image] =>[orig_patent_app_number] => 811909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845999 [patent_doc_number] => 05815464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Address transition detection circuit' [patent_app_type] => 1 [patent_app_number] => 8/811869 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4350 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815464.pdf [firstpage_image] =>[orig_patent_app_number] => 811869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3843989 [patent_doc_number] => 05740123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Semiconductor integrated circuit for changing pulse width according to frequency of external signal' [patent_app_type] => 1 [patent_app_number] => 8/808907 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 10134 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740123.pdf [firstpage_image] =>[orig_patent_app_number] => 808907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3753330 [patent_doc_number] => 05754479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Distributed bit switch logically interleaved for block write performance' [patent_app_type] => 1 [patent_app_number] => 8/808268 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754479.pdf [firstpage_image] =>[orig_patent_app_number] => 808268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3798593 [patent_doc_number] => 05737271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Semiconductor memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/808205 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1914 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737271.pdf [firstpage_image] =>[orig_patent_app_number] => 808205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845535 [patent_doc_number] => 05815438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Optimized biasing scheme for NAND read and hot-carrier write operations' [patent_app_type] => 1 [patent_app_number] => 8/810170 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815438.pdf [firstpage_image] =>[orig_patent_app_number] => 810170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3739378 [patent_doc_number] => 05703832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 't.sub.RAS protection circuit' [patent_app_type] => 1 [patent_app_number] => 8/808267 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2906 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703832.pdf [firstpage_image] =>[orig_patent_app_number] => 808267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853638 [patent_doc_number] => 05745403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'System and method for mitigating imprint effect in ferroelectric random access memories utilizing a complementary data path' [patent_app_type] => 1 [patent_app_number] => 8/810608 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5569 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745403.pdf [firstpage_image] =>[orig_patent_app_number] => 810608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3889441 [patent_doc_number] => 05825694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line' [patent_app_type] => 1 [patent_app_number] => 8/807007 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2107 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825694.pdf [firstpage_image] =>[orig_patent_app_number] => 807007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3837724 [patent_doc_number] => 05784324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Single-chip memory system having a multiple bit line structure for outputting a plurality of data simultaneously' [patent_app_type] => 1 [patent_app_number] => 8/806667 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4231 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784324.pdf [firstpage_image] =>[orig_patent_app_number] => 806667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3783756 [patent_doc_number] => 05774393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Semiconductor memory device capable of operating at high speed and stably even low power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/806176 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8195 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774393.pdf [firstpage_image] =>[orig_patent_app_number] => 806176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836299 [patent_doc_number] => 05732040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Multibit DRAM' [patent_app_type] => 1 [patent_app_number] => 8/800509 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732040.pdf [firstpage_image] =>[orig_patent_app_number] => 800509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757060 [patent_doc_number] => 05717654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Burst EDO memory device with maximized write cycle timing' [patent_app_type] => 1 [patent_app_number] => 8/797339 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7541 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717654.pdf [firstpage_image] =>[orig_patent_app_number] => 797339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3801611 [patent_doc_number] => 05781054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Digital phase correcting apparatus' [patent_app_type] => 1 [patent_app_number] => 8/797895 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1170 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781054.pdf [firstpage_image] =>[orig_patent_app_number] => 797895 [rel_patent_id] =>[rel_patent_doc_number] =>)