Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3790264 [patent_doc_number] => 05757716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Integrated circuit memory devices and methods including programmable block disabling and programmable block selection' [patent_app_type] => 1 [patent_app_number] => 8/766370 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3419 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757716.pdf [firstpage_image] =>[orig_patent_app_number] => 766370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766370
Integrated circuit memory devices and methods including programmable block disabling and programmable block selection Dec 11, 1996 Issued
Array ( [id] => 3747507 [patent_doc_number] => 05699311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/763667 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 11670 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699311.pdf [firstpage_image] =>[orig_patent_app_number] => 763667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763667
Semiconductor memory device Dec 10, 1996 Issued
Array ( [id] => 3892601 [patent_doc_number] => 05748550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Multiple power line arrangement for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/759567 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1367 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748550.pdf [firstpage_image] =>[orig_patent_app_number] => 759567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759567
Multiple power line arrangement for a semiconductor memory device Dec 3, 1996 Issued
Array ( [id] => 3780798 [patent_doc_number] => 05734609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 8/757266 [patent_app_country] => US [patent_app_date] => 1996-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6881 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734609.pdf [firstpage_image] =>[orig_patent_app_number] => 757266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757266
Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same Nov 28, 1996 Issued
Array ( [id] => 3852193 [patent_doc_number] => 05708624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method and structure for controlling internal operations of a DRAM array' [patent_app_type] => 1 [patent_app_number] => 8/757866 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708624.pdf [firstpage_image] =>[orig_patent_app_number] => 757866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757866
Method and structure for controlling internal operations of a DRAM array Nov 26, 1996 Issued
Array ( [id] => 3666658 [patent_doc_number] => 05659497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Signal processing apparatus for processing a plurality of individual signals' [patent_app_type] => 1 [patent_app_number] => 8/757231 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4061 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659497.pdf [firstpage_image] =>[orig_patent_app_number] => 757231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757231
Signal processing apparatus for processing a plurality of individual signals Nov 26, 1996 Issued
Array ( [id] => 3666824 [patent_doc_number] => 05659507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Clock synchronous type DRAM with data latch' [patent_app_type] => 1 [patent_app_number] => 8/753432 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8314 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659507.pdf [firstpage_image] =>[orig_patent_app_number] => 753432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753432
Clock synchronous type DRAM with data latch Nov 24, 1996 Issued
Array ( [id] => 3638897 [patent_doc_number] => 05687125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Semiconductor memory device having redundancy memory cells incorporated into sub memory cell blocks' [patent_app_type] => 1 [patent_app_number] => 8/755366 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4062 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687125.pdf [firstpage_image] =>[orig_patent_app_number] => 755366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755366
Semiconductor memory device having redundancy memory cells incorporated into sub memory cell blocks Nov 24, 1996 Issued
Array ( [id] => 3807997 [patent_doc_number] => 05781493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device having block write function' [patent_app_type] => 1 [patent_app_number] => 8/754368 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3726 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781493.pdf [firstpage_image] =>[orig_patent_app_number] => 754368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754368
Semiconductor memory device having block write function Nov 21, 1996 Issued
Array ( [id] => 3851757 [patent_doc_number] => 05708597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Structure and method for implementing a memory system having a plurality of memory blocks' [patent_app_type] => 1 [patent_app_number] => 8/752868 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8689 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708597.pdf [firstpage_image] =>[orig_patent_app_number] => 752868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752868
Structure and method for implementing a memory system having a plurality of memory blocks Nov 19, 1996 Issued
Array ( [id] => 3792408 [patent_doc_number] => 05818781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Automatic voltage detection in multiple voltage applications' [patent_app_type] => 1 [patent_app_number] => 8/748867 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5352 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818781.pdf [firstpage_image] =>[orig_patent_app_number] => 748867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748867
Automatic voltage detection in multiple voltage applications Nov 12, 1996 Issued
Array ( [id] => 3825234 [patent_doc_number] => 05812483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Integrated circuit memory devices including split word lines and predecoders and related methods' [patent_app_type] => 1 [patent_app_number] => 8/744441 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812483.pdf [firstpage_image] =>[orig_patent_app_number] => 744441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744441
Integrated circuit memory devices including split word lines and predecoders and related methods Nov 7, 1996 Issued
Array ( [id] => 4054457 [patent_doc_number] => 05875129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Nonvolatile semiconductor memory device including potential generating circuit' [patent_app_type] => 1 [patent_app_number] => 8/744821 [patent_app_country] => US [patent_app_date] => 1996-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4736 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875129.pdf [firstpage_image] =>[orig_patent_app_number] => 744821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744821
Nonvolatile semiconductor memory device including potential generating circuit Nov 5, 1996 Issued
Array ( [id] => 3631223 [patent_doc_number] => 05689472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'System and method for providing efficient access to a memory bank' [patent_app_type] => 1 [patent_app_number] => 8/739868 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2347 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689472.pdf [firstpage_image] =>[orig_patent_app_number] => 739868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739868
System and method for providing efficient access to a memory bank Oct 30, 1996 Issued
Array ( [id] => 3756558 [patent_doc_number] => 05717624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Analog memory circuit and method for recording analog signal' [patent_app_type] => 1 [patent_app_number] => 8/739867 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 41 [patent_no_of_words] => 24894 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717624.pdf [firstpage_image] =>[orig_patent_app_number] => 739867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739867
Analog memory circuit and method for recording analog signal Oct 30, 1996 Issued
Array ( [id] => 4077798 [patent_doc_number] => 05867441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/739982 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 11060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867441.pdf [firstpage_image] =>[orig_patent_app_number] => 739982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739982
Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor intergrated circuit, and semiconductor memory Oct 29, 1996 Issued
Array ( [id] => 3851830 [patent_doc_number] => 05708602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Non-volatile semiconductor memory device and method for verifying operating of the same' [patent_app_type] => 1 [patent_app_number] => 8/740567 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 10892 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708602.pdf [firstpage_image] =>[orig_patent_app_number] => 740567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/740567
Non-volatile semiconductor memory device and method for verifying operating of the same Oct 29, 1996 Issued
Array ( [id] => 4077798 [patent_doc_number] => 05867441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/739982 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 11060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867441.pdf [firstpage_image] =>[orig_patent_app_number] => 739982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739982
Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor intergrated circuit, and semiconductor memory Oct 29, 1996 Issued
Array ( [id] => 4077798 [patent_doc_number] => 05867441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/739982 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 11060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867441.pdf [firstpage_image] =>[orig_patent_app_number] => 739982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739982
Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory Oct 29, 1996 Issued
Array ( [id] => 4077798 [patent_doc_number] => 05867441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/739982 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 11060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867441.pdf [firstpage_image] =>[orig_patent_app_number] => 739982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739982
Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory Oct 29, 1996 Issued
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