Search

Vu Anh Le

Examiner (ID: 5941, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2824, 0, 2825, 2511, 2818
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15872955 [patent_doc_number] => 20200143881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/676330 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676330
Transient current-protected threshold switching devices systems and methods Nov 5, 2019 Issued
Array ( [id] => 16865622 [patent_doc_number] => 11024373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Voltage-mode bit line precharge for random-access memory cells [patent_app_type] => utility [patent_app_number] => 16/670633 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4156 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670633
Voltage-mode bit line precharge for random-access memory cells Oct 30, 2019 Issued
Array ( [id] => 16811808 [patent_doc_number] => 20210134363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Mux Decoder with Polarity Transition Capability [patent_app_type] => utility [patent_app_number] => 16/668549 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668549
Mux decoder with polarity transition capability Oct 29, 2019 Issued
Array ( [id] => 16707465 [patent_doc_number] => 10957407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Calculating corrective read voltage offsets in non-volatile random access memory [patent_app_type] => utility [patent_app_number] => 16/669241 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16979 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669241
Calculating corrective read voltage offsets in non-volatile random access memory Oct 29, 2019 Issued
Array ( [id] => 15743293 [patent_doc_number] => 20200110535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => CLOCK MODE DETERMINATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/654477 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654477
Clock mode determination in a memory system Oct 15, 2019 Issued
Array ( [id] => 16119285 [patent_doc_number] => 20200211665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/597251 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597251
Memory system and operating method thereof Oct 8, 2019 Issued
Array ( [id] => 17002325 [patent_doc_number] => 11081147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Pseudo-cryogenic semiconductor device having pseudo-cryogenic temperature sensor and voltage supplier and pseudo-cryogenic semiconductor stack [patent_app_type] => utility [patent_app_number] => 16/596319 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596319 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596319
Pseudo-cryogenic semiconductor device having pseudo-cryogenic temperature sensor and voltage supplier and pseudo-cryogenic semiconductor stack Oct 7, 2019 Issued
Array ( [id] => 16495480 [patent_doc_number] => 10861527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Systems and methods for optimizing magnetic torque and pulse shaping for reducing write error rate in magnetoelectric random access memory [patent_app_type] => utility [patent_app_number] => 16/591293 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 41 [patent_no_of_words] => 11875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591293
Systems and methods for optimizing magnetic torque and pulse shaping for reducing write error rate in magnetoelectric random access memory Oct 1, 2019 Issued
Array ( [id] => 16788986 [patent_doc_number] => 10991423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) [patent_app_type] => utility [patent_app_number] => 16/583039 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 17315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583039
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Sep 24, 2019 Issued
Array ( [id] => 15369255 [patent_doc_number] => 20200020392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => FLYING AND TWISTED BIT LINE ARCHITECTURE FOR DUAL-PORT STATIC RANDOM-ACCESS MEMORY (DP SRAM) [patent_app_type] => utility [patent_app_number] => 16/583060 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583060
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Sep 24, 2019 Issued
Array ( [id] => 16432690 [patent_doc_number] => 10832783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Data sensing device and data sensing method thereof [patent_app_type] => utility [patent_app_number] => 16/581589 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3668 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581589
Data sensing device and data sensing method thereof Sep 23, 2019 Issued
Array ( [id] => 15687497 [patent_doc_number] => 20200098412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MEMRISTOR CIRCUIT, MEMRISTOR CONTROL SYSTEM, ANALOG PRODUCT-SUM OPERATOR, AND NEUROMORPHIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/577067 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577067
Memristor circuit, memristor control system, analog product-sum operator, and neuromorphic device Sep 19, 2019 Issued
Array ( [id] => 15351087 [patent_doc_number] => 20200013435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/573635 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573635
Semiconductor memory device Sep 16, 2019 Issued
Array ( [id] => 16715348 [patent_doc_number] => 20210082495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/572625 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572625
Integrated circuit and operating method thereof Sep 16, 2019 Issued
Array ( [id] => 16315865 [patent_doc_number] => 20200294603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/568555 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568555
Semiconductor memory device Sep 11, 2019 Issued
Array ( [id] => 16119263 [patent_doc_number] => 20200211654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/565625 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565625
Memory system Sep 9, 2019 Issued
Array ( [id] => 16593653 [patent_doc_number] => 10902929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-26 [patent_title] => Zone swapping for wear leveling memory [patent_app_type] => utility [patent_app_number] => 16/555903 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555903 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555903
Zone swapping for wear leveling memory Aug 28, 2019 Issued
Array ( [id] => 16566648 [patent_doc_number] => 10892022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Responding to power loss [patent_app_type] => utility [patent_app_number] => 16/553449 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553449
Responding to power loss Aug 27, 2019 Issued
Array ( [id] => 16738713 [patent_doc_number] => 10964374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Apparatuses and methods for dynamic refresh allocation [patent_app_type] => utility [patent_app_number] => 16/549411 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549411
Apparatuses and methods for dynamic refresh allocation Aug 22, 2019 Issued
Array ( [id] => 16738713 [patent_doc_number] => 10964374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Apparatuses and methods for dynamic refresh allocation [patent_app_type] => utility [patent_app_number] => 16/549411 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549411
Apparatuses and methods for dynamic refresh allocation Aug 22, 2019 Issued
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