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Array ( [id] => 3892391 [patent_doc_number] => 05748535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Advanced program verify for page mode flash memory' [patent_app_type] => 1 [patent_app_number] => 8/612968 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10505 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748535.pdf [firstpage_image] =>[orig_patent_app_number] => 612968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3866952 [patent_doc_number] => 05768196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Shift-register based row select circuit with redundancy for a FIFO memory' [patent_app_type] => 1 [patent_app_number] => 8/609852 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768196.pdf [firstpage_image] =>[orig_patent_app_number] => 609852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3739301 [patent_doc_number] => 05703827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method and structure for generating a boosted word line voltage and a back bias voltage for a memory array' [patent_app_type] => 1 [patent_app_number] => 8/610108 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703827.pdf [firstpage_image] =>[orig_patent_app_number] => 610108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867763 [patent_doc_number] => 05706239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Rechargeable SRAM/flash PCMCIA card' [patent_app_type] => 1 [patent_app_number] => 8/607609 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2940 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706239.pdf [firstpage_image] =>[orig_patent_app_number] => 607609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3659246 [patent_doc_number] => 05606524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Non-volatile semiconductor memory device capable of effecting high-speed operation with low voltage' [patent_app_type] => 1 [patent_app_number] => 8/604830 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 2975 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606524.pdf [firstpage_image] =>[orig_patent_app_number] => 604830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3638661 [patent_doc_number] => 05687110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Array having an update circuit for updating a storage location with a value stored in another storage location' [patent_app_type] => 1 [patent_app_number] => 8/603802 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687110.pdf [firstpage_image] =>[orig_patent_app_number] => 603802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3733167 [patent_doc_number] => 05673230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Semiconductor memory device capable of operating at high speed and stably even under low power supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/602666 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8194 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673230.pdf [firstpage_image] =>[orig_patent_app_number] => 602666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3843651 [patent_doc_number] => 05740099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Semiconductor memory device having peripheral circuit and interface circuit fabricated on bulk region out of silicon-on-insulator region for memory cells' [patent_app_type] => 1 [patent_app_number] => 8/596567 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7478 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740099.pdf [firstpage_image] =>[orig_patent_app_number] => 596567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3703722 [patent_doc_number] => 05661683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'On-chip positive and negative high voltage wordline x-decoding for EPROM/FLASH' [patent_app_type] => 1 [patent_app_number] => 8/596527 [patent_app_country] => US [patent_app_date] => 1996-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3837 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661683.pdf [firstpage_image] =>[orig_patent_app_number] => 596527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3629554 [patent_doc_number] => 05642310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'System and method for controlling source current and voltage during flash memory erase operations' [patent_app_type] => 1 [patent_app_number] => 8/596432 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642310.pdf [firstpage_image] =>[orig_patent_app_number] => 596432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633249 [patent_doc_number] => 05602783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Memory device output buffer' [patent_app_type] => 1 [patent_app_number] => 8/595370 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4158 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 641 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602783.pdf [firstpage_image] =>[orig_patent_app_number] => 595370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3706795 [patent_doc_number] => 05677876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Flash EEPROM with impurity diffused layer in channel area and process of production of same' [patent_app_type] => 1 [patent_app_number] => 8/593369 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2512 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677876.pdf [firstpage_image] =>[orig_patent_app_number] => 593369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250576 [patent_doc_number] => 06144594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Test mode activation and data override' [patent_app_type] => 1 [patent_app_number] => 8/587709 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5696 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144594.pdf [firstpage_image] =>[orig_patent_app_number] => 587709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3635371 [patent_doc_number] => 05608688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'DRAM having output control circuit' [patent_app_type] => 1 [patent_app_number] => 8/588170 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 25 [patent_no_of_words] => 3196 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608688.pdf [firstpage_image] =>[orig_patent_app_number] => 588170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3632972 [patent_doc_number] => 05612919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method of testing an operation of a semiconductor memory device and semiconductor memory device which can be subjected to such an operation test' [patent_app_type] => 1 [patent_app_number] => 8/587683 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 7564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612919.pdf [firstpage_image] =>[orig_patent_app_number] => 587683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3644756 [patent_doc_number] => 05610868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/581967 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11525 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610868.pdf [firstpage_image] =>[orig_patent_app_number] => 581967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672320 [patent_doc_number] => 05625585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Bit line structure with bit line pass over configuration' [patent_app_type] => 1 [patent_app_number] => 8/580270 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2280 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625585.pdf [firstpage_image] =>[orig_patent_app_number] => 580270 [rel_patent_id] =>[rel_patent_doc_number] =>)