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Array ( [id] => 3659125 [patent_doc_number] => 05684741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Auto-verification of programming flash memory cells' [patent_app_type] => 1 [patent_app_number] => 8/578505 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3961 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684741.pdf [firstpage_image] =>[orig_patent_app_number] => 578505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3741326 [patent_doc_number] => 05636172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Reduced pitch laser redundancy fuse bank structure' [patent_app_type] => 1 [patent_app_number] => 8/577468 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3111 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636172.pdf [firstpage_image] =>[orig_patent_app_number] => 577468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672398 [patent_doc_number] => 05625590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/574970 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 12448 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625590.pdf [firstpage_image] =>[orig_patent_app_number] => 574970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3629733 [patent_doc_number] => 05642323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Semiconductor integrated circuit with a data transmission circuit' [patent_app_type] => 1 [patent_app_number] => 8/573076 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 11073 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642323.pdf [firstpage_image] =>[orig_patent_app_number] => 573076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3704476 [patent_doc_number] => 05680366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/573133 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 38 [patent_no_of_words] => 11067 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680366.pdf [firstpage_image] =>[orig_patent_app_number] => 573133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867844 [patent_doc_number] => 05706245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Word line decoding circuit of a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/573967 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2234 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706245.pdf [firstpage_image] =>[orig_patent_app_number] => 573967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657041 [patent_doc_number] => 05629889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions' [patent_app_type] => 1 [patent_app_number] => 8/572483 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629889.pdf [firstpage_image] =>[orig_patent_app_number] => 572483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3733225 [patent_doc_number] => 05673234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Read bitline writer for fallthru in FIFO\'s' [patent_app_type] => 1 [patent_app_number] => 8/572181 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2843 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673234.pdf [firstpage_image] =>[orig_patent_app_number] => 572181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3703654 [patent_doc_number] => 05661678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Semiconductor memory device using dynamic type memory cells' [patent_app_type] => 1 [patent_app_number] => 8/570966 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 63 [patent_no_of_words] => 8836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661678.pdf [firstpage_image] =>[orig_patent_app_number] => 570966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3712898 [patent_doc_number] => 05675538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Non-volatile semiconductor memory device having a reference voltage applied to a sense line after data read out is complete' [patent_app_type] => 1 [patent_app_number] => 8/570870 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1932 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675538.pdf [firstpage_image] =>[orig_patent_app_number] => 570870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3727754 [patent_doc_number] => 05617366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Method and apparatus for a test control circuit of a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/570868 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3726 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617366.pdf [firstpage_image] =>[orig_patent_app_number] => 570868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697669 [patent_doc_number] => 05644534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Voltage booster circuit with plural booster units having outputs connected in common' [patent_app_type] => 1 [patent_app_number] => 8/570682 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3041 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644534.pdf [firstpage_image] =>[orig_patent_app_number] => 570682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3704696 [patent_doc_number] => 05596538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/566668 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4120 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596538.pdf [firstpage_image] =>[orig_patent_app_number] => 566668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3659100 [patent_doc_number] => 05684739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Apparatus and method for determining current or voltage of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/565168 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 6013 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684739.pdf [firstpage_image] =>[orig_patent_app_number] => 565168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247089 [patent_doc_number] => 06118690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Dual storage cell memory' [patent_app_type] => 1 [patent_app_number] => 8/563152 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3260 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118690.pdf [firstpage_image] =>[orig_patent_app_number] => 563152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3611531 [patent_doc_number] => 05579171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Zoom lens equipped with the image stabilizing function' [patent_app_type] => 1 [patent_app_number] => 8/563908 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12245 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579171.pdf [firstpage_image] =>[orig_patent_app_number] => 563908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3671442 [patent_doc_number] => 05657268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Array-source line, bitline and wordline sequence in flash operations' [patent_app_type] => 1 [patent_app_number] => 8/560670 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2328 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657268.pdf [firstpage_image] =>[orig_patent_app_number] => 560670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3617761 [patent_doc_number] => 05590068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Ultra-high density alternate metal virtual ground ROM' [patent_app_type] => 1 [patent_app_number] => 8/555257 [patent_app_country] => US [patent_app_date] => 1995-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2695 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 550 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590068.pdf [firstpage_image] =>[orig_patent_app_number] => 555257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3560621 [patent_doc_number] => 05572458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Multi-level vROM programming method and circuit' [patent_app_type] => 1 [patent_app_number] => 8/552686 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572458.pdf [firstpage_image] =>[orig_patent_app_number] => 552686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3669131 [patent_doc_number] => 05592414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Memory cell circuit independently controlled in writing and reading' [patent_app_type] => 1 [patent_app_number] => 8/547784 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3894 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592414.pdf [firstpage_image] =>[orig_patent_app_number] => 547784 [rel_patent_id] =>[rel_patent_doc_number] =>)