Vu Anh Le

Array ( [id] => 3526969 [patent_doc_number] => 05577000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => 1 [patent_app_number] => 8/458482 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5888 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577000.pdf [firstpage_image] =>[orig_patent_app_number] => 458482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3699141 [patent_doc_number] => 05604704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Compound semiconductor static random access memory device equipped with precharging circuit controlled by boosted signal' [patent_app_type] => 1 [patent_app_number] => 8/450381 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6363 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604704.pdf [firstpage_image] =>[orig_patent_app_number] => 450381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636375 [patent_doc_number] => 05621679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Semiconductor memory device for achieving high bandwidth and method for arranging signal lines therefor' [patent_app_type] => 1 [patent_app_number] => 8/445784 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5898 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621679.pdf [firstpage_image] =>[orig_patent_app_number] => 445784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664493 [patent_doc_number] => 05623445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Semiconductor memory device having data erasing mechanism' [patent_app_type] => 1 [patent_app_number] => 8/440253 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 44 [patent_no_of_words] => 8014 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623445.pdf [firstpage_image] =>[orig_patent_app_number] => 440253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664422 [patent_doc_number] => 05623439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => 1 [patent_app_number] => 8/439780 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4774 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623439.pdf [firstpage_image] =>[orig_patent_app_number] => 439780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3822559 [patent_doc_number] => 05710742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'High density two port SRAM cell for low voltage CMOS applications' [patent_app_type] => 1 [patent_app_number] => 8/440285 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 2559 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710742.pdf [firstpage_image] =>[orig_patent_app_number] => 440285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3678381 [patent_doc_number] => 05600592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied' [patent_app_type] => 1 [patent_app_number] => 8/436563 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4786 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600592.pdf [firstpage_image] =>[orig_patent_app_number] => 436563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3739240 [patent_doc_number] => 05703823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Memory device with programmable self-refreshing and testing methods therefore' [patent_app_type] => 1 [patent_app_number] => 8/435606 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703823.pdf [firstpage_image] =>[orig_patent_app_number] => 435606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705019 [patent_doc_number] => 05619447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Ferro-electric memory array architecture and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 8/433880 [patent_app_country] => US [patent_app_date] => 1995-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4677 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619447.pdf [firstpage_image] =>[orig_patent_app_number] => 433880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3698010 [patent_doc_number] => 05663923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Nonvolatile memory blocking architecture' [patent_app_type] => 1 [patent_app_number] => 8/430882 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5530 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663923.pdf [firstpage_image] =>[orig_patent_app_number] => 430882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3553613 [patent_doc_number] => 05555208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Static random access memory' [patent_app_type] => 1 [patent_app_number] => 8/429778 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2338 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555208.pdf [firstpage_image] =>[orig_patent_app_number] => 429778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544689 [patent_doc_number] => 05557568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells' [patent_app_type] => 1 [patent_app_number] => 8/427265 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 130 [patent_no_of_words] => 13780 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557568.pdf [firstpage_image] =>[orig_patent_app_number] => 427265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3592907 [patent_doc_number] => 05517061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'CMOS read only memory with programming at the second metal layer on a two-metal process' [patent_app_type] => 1 [patent_app_number] => 8/426368 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517061.pdf [firstpage_image] =>[orig_patent_app_number] => 426368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3544883 [patent_doc_number] => 05557581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Logic and memory circuit with reduced input-to-output signal propagation delay' [patent_app_type] => 1 [patent_app_number] => 8/419377 [patent_app_country] => US [patent_app_date] => 1995-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2028 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557581.pdf [firstpage_image] =>[orig_patent_app_number] => 419377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3560693 [patent_doc_number] => 05572463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Nonvolatile semiconductor memory with pre-read means' [patent_app_type] => 1 [patent_app_number] => 8/416281 [patent_app_country] => US [patent_app_date] => 1995-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 167 [patent_no_of_words] => 45947 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572463.pdf [firstpage_image] =>[orig_patent_app_number] => 416281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3516688 [patent_doc_number] => 05570329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'System for selectively inverting a magnetic bias field for magneto-optic recording' [patent_app_type] => 1 [patent_app_number] => 8/414705 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2054 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570329.pdf [firstpage_image] =>[orig_patent_app_number] => 414705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3559434 [patent_doc_number] => 05548551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Negative voltage decoding in non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 8/409779 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7364 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548551.pdf [firstpage_image] =>[orig_patent_app_number] => 409779 [rel_patent_id] =>[rel_patent_doc_number] =>)