Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3608979 [patent_doc_number] => 05559765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Disk drive access controller' [patent_app_type] => 1 [patent_app_number] => 8/406152 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10332 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559765.pdf [firstpage_image] =>[orig_patent_app_number] => 406152 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406152
Disk drive access controller Mar 16, 1995 Issued
Array ( [id] => 3549705 [patent_doc_number] => 05481499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Integrated matrix memory, comprising a circuit arrangement for testing the addressing' [patent_app_type] => 1 [patent_app_number] => 8/405566 [patent_app_country] => US [patent_app_date] => 1995-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5037 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481499.pdf [firstpage_image] =>[orig_patent_app_number] => 405566 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/405566
Integrated matrix memory, comprising a circuit arrangement for testing the addressing Mar 15, 1995 Issued
Array ( [id] => 3566291 [patent_doc_number] => 05544124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Optimization circuitry and control for a synchronous memory device with programmable latency period' [patent_app_type] => 1 [patent_app_number] => 8/403382 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4225 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544124.pdf [firstpage_image] =>[orig_patent_app_number] => 403382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403382
Optimization circuitry and control for a synchronous memory device with programmable latency period Mar 12, 1995 Issued
Array ( [id] => 3706961 [patent_doc_number] => 05677887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Semiconductor memory device having a large storage capacity and a high speed operation' [patent_app_type] => 1 [patent_app_number] => 8/401693 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 39 [patent_no_of_words] => 5702 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677887.pdf [firstpage_image] =>[orig_patent_app_number] => 401693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401693
Semiconductor memory device having a large storage capacity and a high speed operation Mar 9, 1995 Issued
Array ( [id] => 3515641 [patent_doc_number] => 05515326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing' [patent_app_type] => 1 [patent_app_number] => 8/402221 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 69 [patent_no_of_words] => 37618 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515326.pdf [firstpage_image] =>[orig_patent_app_number] => 402221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402221
Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing Mar 9, 1995 Issued
Array ( [id] => 3588135 [patent_doc_number] => 05491655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode' [patent_app_type] => 1 [patent_app_number] => 8/402218 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 69 [patent_no_of_words] => 37618 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491655.pdf [firstpage_image] =>[orig_patent_app_number] => 402218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402218
Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode Mar 9, 1995 Issued
Array ( [id] => 3527095 [patent_doc_number] => 05506805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Static semiconductor memory device having circuitry for enlarging write recovery margin' [patent_app_type] => 1 [patent_app_number] => 8/402212 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 69 [patent_no_of_words] => 37621 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506805.pdf [firstpage_image] =>[orig_patent_app_number] => 402212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/402212
Static semiconductor memory device having circuitry for enlarging write recovery margin Mar 9, 1995 Issued
Array ( [id] => 3438095 [patent_doc_number] => 05463579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Semiconductor memory device with floating gate and method for driving the same' [patent_app_type] => 1 [patent_app_number] => 8/401306 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4911 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463579.pdf [firstpage_image] =>[orig_patent_app_number] => 401306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401306
Semiconductor memory device with floating gate and method for driving the same Mar 8, 1995 Issued
Array ( [id] => 3563245 [patent_doc_number] => 05574695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Semiconductor memory device with bit line load circuit for high speed operation' [patent_app_type] => 1 [patent_app_number] => 8/397678 [patent_app_country] => US [patent_app_date] => 1995-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7824 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574695.pdf [firstpage_image] =>[orig_patent_app_number] => 397678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/397678
Semiconductor memory device with bit line load circuit for high speed operation Mar 1, 1995 Issued
Array ( [id] => 3602725 [patent_doc_number] => 05521858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/374779 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9804 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521858.pdf [firstpage_image] =>[orig_patent_app_number] => 374779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/374779
Semiconductor device Feb 27, 1995 Issued
Array ( [id] => 3504665 [patent_doc_number] => 05508954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Method and apparatus for reduced fatigue in ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/395582 [patent_app_country] => US [patent_app_date] => 1995-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6898 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508954.pdf [firstpage_image] =>[orig_patent_app_number] => 395582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395582
Method and apparatus for reduced fatigue in ferroelectric memory Feb 26, 1995 Issued
Array ( [id] => 3608634 [patent_doc_number] => 05559742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Flash memory having transistor redundancy' [patent_app_type] => 1 [patent_app_number] => 8/393578 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559742.pdf [firstpage_image] =>[orig_patent_app_number] => 393578 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393578
Flash memory having transistor redundancy Feb 22, 1995 Issued
Array ( [id] => 3669228 [patent_doc_number] => 05592421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Semiconductor integrated circuit for generating an internal power source voltage with reduced potential changes' [patent_app_type] => 1 [patent_app_number] => 8/393077 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 9215 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592421.pdf [firstpage_image] =>[orig_patent_app_number] => 393077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393077
Semiconductor integrated circuit for generating an internal power source voltage with reduced potential changes Feb 22, 1995 Issued
Array ( [id] => 3507521 [patent_doc_number] => 05532956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Memory cell structure for semiconductor device and dynamic semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/392477 [patent_app_country] => US [patent_app_date] => 1995-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6899 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532956.pdf [firstpage_image] =>[orig_patent_app_number] => 392477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/392477
Memory cell structure for semiconductor device and dynamic semiconductor memory device Feb 21, 1995 Issued
Array ( [id] => 3582627 [patent_doc_number] => 05539703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Dynamic memory device including apparatus for controlling refresh cycle time' [patent_app_type] => 1 [patent_app_number] => 8/395369 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4964 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539703.pdf [firstpage_image] =>[orig_patent_app_number] => 395369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395369
Dynamic memory device including apparatus for controlling refresh cycle time Feb 20, 1995 Issued
Array ( [id] => 3507764 [patent_doc_number] => 05532972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Method and circuit for timing the reading of nonvolatile memories' [patent_app_type] => 1 [patent_app_number] => 8/391920 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6051 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532972.pdf [firstpage_image] =>[orig_patent_app_number] => 391920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/391920
Method and circuit for timing the reading of nonvolatile memories Feb 20, 1995 Issued
Array ( [id] => 3566945 [patent_doc_number] => 05502680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Sense amplifier with pull-up circuit for accelerated latching of logic level output data' [patent_app_type] => 1 [patent_app_number] => 8/389293 [patent_app_country] => US [patent_app_date] => 1995-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502680.pdf [firstpage_image] =>[orig_patent_app_number] => 389293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389293
Sense amplifier with pull-up circuit for accelerated latching of logic level output data Feb 15, 1995 Issued
Array ( [id] => 3644702 [patent_doc_number] => 05610864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Burst EDO memory device with maximized write cycle timing' [patent_app_type] => 1 [patent_app_number] => 8/386894 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610864.pdf [firstpage_image] =>[orig_patent_app_number] => 386894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386894
Burst EDO memory device with maximized write cycle timing Feb 9, 1995 Issued
08/384976 MEMORY DEVICE HAVING POTENTIAL CONTROL FOR INCREASING THE OPERATING MARGIN AT THE START OF A SENSING CYCLE Feb 6, 1995 Abandoned
Array ( [id] => 3482505 [patent_doc_number] => 05477498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/385016 [patent_app_country] => US [patent_app_date] => 1995-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 52 [patent_no_of_words] => 11132 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477498.pdf [firstpage_image] =>[orig_patent_app_number] => 385016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/385016
Semiconductor memory device Feb 6, 1995 Issued
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