Search

Vu Anh Le

Examiner (ID: 5941, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2824, 0, 2825, 2511, 2818
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16738713 [patent_doc_number] => 10964374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Apparatuses and methods for dynamic refresh allocation [patent_app_type] => utility [patent_app_number] => 16/549411 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549411
Apparatuses and methods for dynamic refresh allocation Aug 22, 2019 Issued
Array ( [id] => 16738713 [patent_doc_number] => 10964374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Apparatuses and methods for dynamic refresh allocation [patent_app_type] => utility [patent_app_number] => 16/549411 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549411
Apparatuses and methods for dynamic refresh allocation Aug 22, 2019 Issued
Array ( [id] => 16020373 [patent_doc_number] => 20200185030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => MEMORY DEVICE PERFORMING DATA COMPARISON WRITE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/545765 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545765
Memory device performing data comparison write and memory system including the same Aug 19, 2019 Issued
Array ( [id] => 16528489 [patent_doc_number] => 20200402570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SRAM BITCELL SUPPLY BLOCK WITH MULTIPLE OPERATING MODES [patent_app_type] => utility [patent_app_number] => 16/543507 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543507
SRAM bitcell supply block with multiple operating modes Aug 15, 2019 Issued
Array ( [id] => 17165955 [patent_doc_number] => 11152063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Writing multiple levels in a phase change memory [patent_app_type] => utility [patent_app_number] => 16/526303 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526303 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526303
Writing multiple levels in a phase change memory Jul 29, 2019 Issued
Array ( [id] => 16668243 [patent_doc_number] => 10937496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Writing multiple levels in a phase change memory [patent_app_type] => utility [patent_app_number] => 16/526273 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14044 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526273
Writing multiple levels in a phase change memory Jul 29, 2019 Issued
Array ( [id] => 15122963 [patent_doc_number] => 20190348115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => FAST READ SPEED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/521126 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521126
Fast read speed memory device Jul 23, 2019 Issued
Array ( [id] => 16463867 [patent_doc_number] => 10847224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Low power and area ternary content addressable memory circuit [patent_app_type] => utility [patent_app_number] => 16/520243 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520243
Low power and area ternary content addressable memory circuit Jul 22, 2019 Issued
Array ( [id] => 16409781 [patent_doc_number] => 10818344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Artificial neural network functionality using dynamic random-access memory [patent_app_type] => utility [patent_app_number] => 16/517807 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13874 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517807
Artificial neural network functionality using dynamic random-access memory Jul 21, 2019 Issued
Array ( [id] => 16723499 [patent_doc_number] => 20210090646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MULTIPLIER AND OPERATION METHOD BASED ON 1T1R MEMORY [patent_app_type] => utility [patent_app_number] => 16/971678 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/971678
Multiplier and operation method based on 1T1R memory Jul 11, 2019 Issued
Array ( [id] => 16264337 [patent_doc_number] => 10755778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Semiconductor switch and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/507077 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 11186 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507077
Semiconductor switch and semiconductor device Jul 9, 2019 Issued
Array ( [id] => 15029861 [patent_doc_number] => 20190325935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/503935 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503935 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503935
Semiconductor memory device and operating method thereof Jul 4, 2019 Issued
Array ( [id] => 16495502 [patent_doc_number] => 10861549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Ternary content addressable memory unit capable of reducing charge sharing effect [patent_app_type] => utility [patent_app_number] => 16/503617 [patent_app_country] => US [patent_app_date] => 2019-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3186 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503617
Ternary content addressable memory unit capable of reducing charge sharing effect Jul 3, 2019 Issued
Array ( [id] => 16432699 [patent_doc_number] => 10832792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Apparatuses and methods for adjusting victim data [patent_app_type] => utility [patent_app_number] => 16/459507 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459507
Apparatuses and methods for adjusting victim data Jun 30, 2019 Issued
Array ( [id] => 16218257 [patent_doc_number] => 10734077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => Word line discharge skip for faster read time [patent_app_type] => utility [patent_app_number] => 16/456029 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 13068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456029
Word line discharge skip for faster read time Jun 27, 2019 Issued
Array ( [id] => 16047685 [patent_doc_number] => 10685721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Apparatuses and methods for charging a global access line prior to accessing a memory [patent_app_type] => utility [patent_app_number] => 16/454263 [patent_app_country] => US [patent_app_date] => 2019-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16454263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/454263
Apparatuses and methods for charging a global access line prior to accessing a memory Jun 26, 2019 Issued
Array ( [id] => 16233697 [patent_doc_number] => 10741257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Dynamic bit line voltage and sensing time enhanced read for data recovery [patent_app_type] => utility [patent_app_number] => 16/453291 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5655 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453291
Dynamic bit line voltage and sensing time enhanced read for data recovery Jun 25, 2019 Issued
Array ( [id] => 16172629 [patent_doc_number] => 10714205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => Multi-purposed leak detector [patent_app_type] => utility [patent_app_number] => 16/451335 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 61 [patent_no_of_words] => 26065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451335
Multi-purposed leak detector Jun 24, 2019 Issued
Array ( [id] => 14966953 [patent_doc_number] => 20190310955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => METHODS AND DEVICES THAT UTILIZE HARDWARE TO MOVE BLOCKS OF OPERATING PARAMETER DATA FROM MEMORY TO A REGISTER SET [patent_app_type] => utility [patent_app_number] => 16/450905 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450905
Methods and devices that utilize hardware to move blocks of operating parameter data from memory to a register set Jun 23, 2019 Issued
Array ( [id] => 16521439 [patent_doc_number] => 10872662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => 2T2R binary weight cell with high on/off ratio background [patent_app_type] => utility [patent_app_number] => 16/448799 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448799
2T2R binary weight cell with high on/off ratio background Jun 20, 2019 Issued
Menu