Vu Anh Le

Array ( [id] => 3105158 [patent_doc_number] => 05291439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Semiconductor memory cell and memory array with inversion layer' [patent_app_type] => 1 [patent_app_number] => 7/758656 [patent_app_country] => US [patent_app_date] => 1991-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4980 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291439.pdf [firstpage_image] =>[orig_patent_app_number] => 758656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3039618 [patent_doc_number] => 05349565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'SRAM with transparent address latch and unlatched chip enable' [patent_app_type] => 1 [patent_app_number] => 7/755319 [patent_app_country] => US [patent_app_date] => 1991-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2853 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349565.pdf [firstpage_image] =>[orig_patent_app_number] => 755319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3059755 [patent_doc_number] => 05305258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Semiconductor memory and memory cell' [patent_app_type] => 1 [patent_app_number] => 7/751535 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2907 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305258.pdf [firstpage_image] =>[orig_patent_app_number] => 751535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2966233 [patent_doc_number] => 05243576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/752142 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3488 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/243/05243576.pdf [firstpage_image] =>[orig_patent_app_number] => 752142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3032153 [patent_doc_number] => 05289406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Read only memory for storing multi-data' [patent_app_type] => 1 [patent_app_number] => 7/744098 [patent_app_country] => US [patent_app_date] => 1991-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 41 [patent_no_of_words] => 15033 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289406.pdf [firstpage_image] =>[orig_patent_app_number] => 744098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2995961 [patent_doc_number] => 05251168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'Boundary cells for improving retention time in memory devices' [patent_app_type] => 1 [patent_app_number] => 7/738383 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3969 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/251/05251168.pdf [firstpage_image] =>[orig_patent_app_number] => 738383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2958126 [patent_doc_number] => 05222041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Data amplifying system in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/735004 [patent_app_country] => US [patent_app_date] => 1991-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3795 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222041.pdf [firstpage_image] =>[orig_patent_app_number] => 735004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2899299 [patent_doc_number] => 05239501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Static memory cell' [patent_app_type] => 1 [patent_app_number] => 7/735047 [patent_app_country] => US [patent_app_date] => 1991-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3634 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239501.pdf [firstpage_image] =>[orig_patent_app_number] => 735047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2987359 [patent_doc_number] => 05257228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Efficiency improved DRAM row redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 7/701233 [patent_app_country] => US [patent_app_date] => 1991-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2901 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257228.pdf [firstpage_image] =>[orig_patent_app_number] => 701233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2945219 [patent_doc_number] => 05229972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Nonvolatile semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 7/639331 [patent_app_country] => US [patent_app_date] => 1991-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4137 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229972.pdf [firstpage_image] =>[orig_patent_app_number] => 639331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2998524 [patent_doc_number] => 05267214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 7/616264 [patent_app_country] => US [patent_app_date] => 1990-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15133 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/267/05267214.pdf [firstpage_image] =>[orig_patent_app_number] => 616264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3470981 [patent_doc_number] => 05392252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Programmable memory addressing' [patent_app_type] => 1 [patent_app_number] => 7/612293 [patent_app_country] => US [patent_app_date] => 1990-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3141 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392252.pdf [firstpage_image] =>[orig_patent_app_number] => 612293 [rel_patent_id] =>[rel_patent_doc_number] =>)