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Vu Anh Le

Examiner (ID: 5206, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
0, 2818, 2511, 2825, 2824
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16988033 [patent_doc_number] => 11075216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/449286 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 14834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16449286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/449286
Non-volatile memory Jun 20, 2019 Issued
Array ( [id] => 16528473 [patent_doc_number] => 20200402554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SYSTEMS AND METHODS INVOLVING MEMORY-SIDE (NAND-SIDE) WRITE TRAINING TO IMPROVE DATA VALID WINDOWS [patent_app_type] => utility [patent_app_number] => 16/447727 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447727
Systems and methods involving memory-side (NAND-side) write training to improve data valid windows Jun 19, 2019 Issued
Array ( [id] => 15184355 [patent_doc_number] => 20190362769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION [patent_app_type] => utility [patent_app_number] => 16/440015 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440015
Variable width memory module supporting enhanced error detection and correction Jun 12, 2019 Issued
Array ( [id] => 16308482 [patent_doc_number] => 10777287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Memory control apparatus, information processing apparatus, and memory control method [patent_app_type] => utility [patent_app_number] => 16/438727 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4791 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438727
Memory control apparatus, information processing apparatus, and memory control method Jun 11, 2019 Issued
Array ( [id] => 19169983 [patent_doc_number] => 11985909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Fabrication of stackable embedded eDRAM using a binary alloy based on antimony [patent_app_type] => utility [patent_app_number] => 16/435875 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5526 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435875
Fabrication of stackable embedded eDRAM using a binary alloy based on antimony Jun 9, 2019 Issued
Array ( [id] => 14903727 [patent_doc_number] => 20190295629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Systems and Methods for Reducing Standby Power in Floating Body Memory Devices [patent_app_type] => utility [patent_app_number] => 16/435551 [patent_app_country] => US [patent_app_date] => 2019-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435551
Systems and methods for reducing standby power in floating body memory devices Jun 8, 2019 Issued
Array ( [id] => 16432662 [patent_doc_number] => 10832754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Current monitor for a memory device [patent_app_type] => utility [patent_app_number] => 16/433871 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16607 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/433871
Current monitor for a memory device Jun 5, 2019 Issued
Array ( [id] => 16201716 [patent_doc_number] => 10726891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Reducing post-read disturb in a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 16/415457 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 21704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415457
Reducing post-read disturb in a nonvolatile memory device May 16, 2019 Issued
Array ( [id] => 14812527 [patent_doc_number] => 20190272873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => METHOD AND APPARATUS FOR READING RRAM CELL [patent_app_type] => utility [patent_app_number] => 16/413937 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413937
Method and apparatus for reading RRAM cell May 15, 2019 Issued
Array ( [id] => 14784377 [patent_doc_number] => 20190267086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 16/411807 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411807
Writing multiple levels in a phase change memory May 13, 2019 Issued
Array ( [id] => 14784379 [patent_doc_number] => 20190267087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 16/411844 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411844
Writing multiple levels in a phase change memory May 13, 2019 Issued
Array ( [id] => 16308447 [patent_doc_number] => 10777251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => In-memory processing based on combining output currents [patent_app_type] => utility [patent_app_number] => 16/408331 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408331
In-memory processing based on combining output currents May 8, 2019 Issued
Array ( [id] => 16249246 [patent_doc_number] => 10748619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Memory device with different bits per cell on different word lines in a block [patent_app_type] => utility [patent_app_number] => 16/406605 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 21205 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406605
Memory device with different bits per cell on different word lines in a block May 7, 2019 Issued
Array ( [id] => 16172623 [patent_doc_number] => 10714199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => PUF latch for OTP memory arrays and method of operation [patent_app_type] => utility [patent_app_number] => 16/396355 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/396355
PUF latch for OTP memory arrays and method of operation Apr 25, 2019 Issued
Array ( [id] => 15092583 [patent_doc_number] => 20190341103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => NON-VOLATILE MEMORY DEVICE, IN PARTICULAR PHASE CHANGE MEMORY, AND READING METHOD [patent_app_type] => utility [patent_app_number] => 16/393115 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393115 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/393115
Non-volatile memory device, in particular phase change memory, and reading method Apr 23, 2019 Issued
Array ( [id] => 17115317 [patent_doc_number] => 20210295914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/250494 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250494
STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD Apr 17, 2019 Abandoned
Array ( [id] => 16264358 [patent_doc_number] => 10755799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Apparatuses and methods for fuse latch redundancy [patent_app_type] => utility [patent_app_number] => 16/384757 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384757
Apparatuses and methods for fuse latch redundancy Apr 14, 2019 Issued
Array ( [id] => 16132025 [patent_doc_number] => 10699779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Neural network classifier using array of two-gate non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 16/382013 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 7557 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382013
Neural network classifier using array of two-gate non-volatile memory cells Apr 10, 2019 Issued
Array ( [id] => 17326282 [patent_doc_number] => 11217307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Circuit and method for programming resistive memory cells [patent_app_type] => utility [patent_app_number] => 15/733715 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6974 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15733715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/733715
Circuit and method for programming resistive memory cells Apr 4, 2019 Issued
Array ( [id] => 16417597 [patent_doc_number] => 10825497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Semiconductor device including spin-orbit torque line and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/369869 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369869
Semiconductor device including spin-orbit torque line and method of operating the same Mar 28, 2019 Issued
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