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Vu Anh Le

Examiner (ID: 5206, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
0, 2818, 2511, 2825, 2824
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14752515 [patent_doc_number] => 20190259431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/051189 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051189
DFE conditioning for write operations of a memory device Jul 30, 2018 Issued
Array ( [id] => 13613099 [patent_doc_number] => 20180358099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY [patent_app_type] => utility [patent_app_number] => 16/046527 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046527
Apparatuses and methods for charging a global access line prior to accessing a memory Jul 25, 2018 Issued
Array ( [id] => 14919895 [patent_doc_number] => 10431274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/044975 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044975
Semiconductor memory device Jul 24, 2018 Issued
Array ( [id] => 14508911 [patent_doc_number] => 20190198110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/041559 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041559
Semiconductor apparatus Jul 19, 2018 Issued
Array ( [id] => 14063543 [patent_doc_number] => 10236072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Electronic device with a fuse read mechanism [patent_app_type] => utility [patent_app_number] => 16/022549 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7733 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022549
Electronic device with a fuse read mechanism Jun 27, 2018 Issued
Array ( [id] => 15138989 [patent_doc_number] => 10482976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Memory device performing UV-assisted erase operation [patent_app_type] => utility [patent_app_number] => 16/021905 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 13901 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021905
Memory device performing UV-assisted erase operation Jun 27, 2018 Issued
Array ( [id] => 17070411 [patent_doc_number] => 20210272628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DRIVE DEVICE [patent_app_type] => utility [patent_app_number] => 17/255434 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17255434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/255434
Memory drive device Jun 26, 2018 Issued
Array ( [id] => 13740113 [patent_doc_number] => 20180374526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Systems and Methods for Reducing Write Error Rate in Magnetoelectric Random Access Memory Through Pulse Sharpening and Reverse Pulse Schemes [patent_app_type] => utility [patent_app_number] => 16/020933 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020933
Systems and methods for reducing write error rate in magnetoelectric random access memory through pulse sharpening and reverse pulse schemes Jun 26, 2018 Issued
Array ( [id] => 15474817 [patent_doc_number] => 10553291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Nonvolatile memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/015959 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015959
Nonvolatile memory device and operating method thereof Jun 21, 2018 Issued
Array ( [id] => 14221775 [patent_doc_number] => 20190123272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/014871 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014871
Variable resistance memory device and method of manufacturing the same Jun 20, 2018 Issued
Array ( [id] => 14800669 [patent_doc_number] => 10403342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Hybrid flash memory structure [patent_app_type] => utility [patent_app_number] => 16/011673 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4281 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011673
Hybrid flash memory structure Jun 18, 2018 Issued
Array ( [id] => 15704855 [patent_doc_number] => 10608620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Shifter circuits having registers arranged in a folded topology [patent_app_type] => utility [patent_app_number] => 16/012715 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6793 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/012715
Shifter circuits having registers arranged in a folded topology Jun 18, 2018 Issued
Array ( [id] => 14525457 [patent_doc_number] => 10339999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Variable width memory module supporting enhanced error detection and correction [patent_app_type] => utility [patent_app_number] => 16/011539 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011539
Variable width memory module supporting enhanced error detection and correction Jun 17, 2018 Issued
Array ( [id] => 15286003 [patent_doc_number] => 10515670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Memory apparatus and voltage control method thereof [patent_app_type] => utility [patent_app_number] => 16/006871 [patent_app_country] => US [patent_app_date] => 2018-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2667 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006871
Memory apparatus and voltage control method thereof Jun 12, 2018 Issued
Array ( [id] => 15970081 [patent_doc_number] => 20200168792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => PHASE-CHANGE MEMORY DEVICE HAVING REVERSED PHASE-CHANGE CHARACTERISTICS AND PHASE-CHANGE MEMORY HAVING HIGHLY INTEGRATED THREE-DIMENSIONAL ARCHITECTURE USING SAME [patent_app_type] => utility [patent_app_number] => 16/620577 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/620577
Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same May 31, 2018 Issued
Array ( [id] => 15286071 [patent_doc_number] => 10515704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Semiconductor memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/993143 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 12565 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993143
Semiconductor memory device and operating method thereof May 29, 2018 Issued
Array ( [id] => 15731191 [patent_doc_number] => 10614024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor layered device with data bus inversion [patent_app_type] => utility [patent_app_number] => 15/987895 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 13604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987895
Semiconductor layered device with data bus inversion May 22, 2018 Issued
Array ( [id] => 15731191 [patent_doc_number] => 10614024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor layered device with data bus inversion [patent_app_type] => utility [patent_app_number] => 15/987895 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 13604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987895
Semiconductor layered device with data bus inversion May 22, 2018 Issued
Array ( [id] => 15731191 [patent_doc_number] => 10614024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor layered device with data bus inversion [patent_app_type] => utility [patent_app_number] => 15/987895 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 13604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987895
Semiconductor layered device with data bus inversion May 22, 2018 Issued
Array ( [id] => 15731191 [patent_doc_number] => 10614024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor layered device with data bus inversion [patent_app_type] => utility [patent_app_number] => 15/987895 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 13604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987895
Semiconductor layered device with data bus inversion May 22, 2018 Issued
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