
Vu Anh Le
Examiner (ID: 5206, Phone: (571)272-1871 , Office: P/2825 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 0, 2818, 2511, 2825, 2824 |
| Total Applications | 2999 |
| Issued Applications | 2864 |
| Pending Applications | 54 |
| Abandoned Applications | 89 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13145415
[patent_doc_number] => 10090045
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-02
[patent_title] => Programming method of non volatile memory device according to program speed of memory cells
[patent_app_type] => utility
[patent_app_number] => 15/917753
[patent_app_country] => US
[patent_app_date] => 2018-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 64
[patent_no_of_words] => 25286
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917753
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/917753 | Programming method of non volatile memory device according to program speed of memory cells | Mar 10, 2018 | Issued |
Array
(
[id] => 14784369
[patent_doc_number] => 20190267082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => RESISTANCE AND GATE CONTROL IN DECODER CIRCUITS FOR READ AND WRITE OPTIMIZATION
[patent_app_type] => utility
[patent_app_number] => 15/908175
[patent_app_country] => US
[patent_app_date] => 2018-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 31665
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908175
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/908175 | Resistance and gate control in decoder circuits for read and write optimization | Feb 27, 2018 | Issued |
Array
(
[id] => 14063519
[patent_doc_number] => 10236060
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-03-19
[patent_title] => Nonvolatile memory device
[patent_app_type] => utility
[patent_app_number] => 15/906171
[patent_app_country] => US
[patent_app_date] => 2018-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 5657
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906171
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/906171 | Nonvolatile memory device | Feb 26, 2018 | Issued |
Array
(
[id] => 16347757
[patent_doc_number] => 20200312408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => ENERGY EFFICIENT WRITE SCHEME FOR NON-VOLATILE RESISTIVE CROSSBAR ARRAYS WITH SELECTORS
[patent_app_type] => utility
[patent_app_number] => 16/954643
[patent_app_country] => US
[patent_app_date] => 2018-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16954643
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/954643 | Energy efficient write scheme for non-volatile resistive crossbar arrays with selectors | Jan 29, 2018 | Issued |
Array
(
[id] => 14332575
[patent_doc_number] => 10297311
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-05-21
[patent_title] => Systems and methods for memory protocol training
[patent_app_type] => utility
[patent_app_number] => 15/884361
[patent_app_country] => US
[patent_app_date] => 2018-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10880
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884361
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/884361 | Systems and methods for memory protocol training | Jan 29, 2018 | Issued |
Array
(
[id] => 15375321
[patent_doc_number] => 10529386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-07
[patent_title] => Memory control circuit with distributed architecture
[patent_app_type] => utility
[patent_app_number] => 15/879735
[patent_app_country] => US
[patent_app_date] => 2018-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 14070
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879735
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/879735 | Memory control circuit with distributed architecture | Jan 24, 2018 | Issued |
Array
(
[id] => 15046151
[patent_doc_number] => 20190334080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => MEMORY CELL, MEMORY ARRAY, METHOD OF FORMING AND OPERATING MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 16/478195
[patent_app_country] => US
[patent_app_date] => 2018-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27727
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16478195
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/478195 | Memory cell, memory array, method of forming and operating memory cell | Jan 16, 2018 | Issued |
Array
(
[id] => 13292935
[patent_doc_number] => 10157666
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-18
[patent_title] => Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)
[patent_app_type] => utility
[patent_app_number] => 15/871484
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 21
[patent_no_of_words] => 17264
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871484
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871484 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Jan 14, 2018 | Issued |
Array
(
[id] => 14125027
[patent_doc_number] => 10249376
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Flash memory storage device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 15/871107
[patent_app_country] => US
[patent_app_date] => 2018-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3294
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871107
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/871107 | Flash memory storage device and operating method thereof | Jan 14, 2018 | Issued |
Array
(
[id] => 15108357
[patent_doc_number] => 10475508
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-12
[patent_title] => Transient current-protected threshold switching devices systems and methods
[patent_app_type] => utility
[patent_app_number] => 15/854638
[patent_app_country] => US
[patent_app_date] => 2017-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6872
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854638
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/854638 | Transient current-protected threshold switching devices systems and methods | Dec 25, 2017 | Issued |
Array
(
[id] => 14063549
[patent_doc_number] => 10236075
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-03-19
[patent_title] => Predicting tunnel barrier endurance using redundant memory structures
[patent_app_type] => utility
[patent_app_number] => 15/851593
[patent_app_country] => US
[patent_app_date] => 2017-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 12290
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851593
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/851593 | Predicting tunnel barrier endurance using redundant memory structures | Dec 20, 2017 | Issued |
Array
(
[id] => 12649770
[patent_doc_number] => 20180108421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/847531
[patent_app_country] => US
[patent_app_date] => 2017-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847531
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/847531 | Apparatuses and methods for charging a global access line prior to accessing a memory | Dec 18, 2017 | Issued |
Array
(
[id] => 13320343
[patent_doc_number] => 20180211709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-26
[patent_title] => NONVOLATILE MEMORY DEVICE FOR VARYING A RECOVERY SECTION AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/839121
[patent_app_country] => US
[patent_app_date] => 2017-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10725
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839121
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/839121 | Nonvolatile memory device for varying a recovery section and operating method thereof | Dec 11, 2017 | Issued |
Array
(
[id] => 14177455
[patent_doc_number] => 10262748
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-16
[patent_title] => Non-volatile memory and program method thereof
[patent_app_type] => utility
[patent_app_number] => 15/838109
[patent_app_country] => US
[patent_app_date] => 2017-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3006
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838109
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/838109 | Non-volatile memory and program method thereof | Dec 10, 2017 | Issued |
Array
(
[id] => 12917311
[patent_doc_number] => 20180197613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-07-12
[patent_title] => METHOD FOR OPERATING SINGLE-POLY NON-VOLATILE MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 15/834063
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3750
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834063
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/834063 | Method for operating single-poly non-volatile memory cell | Dec 6, 2017 | Issued |
Array
(
[id] => 14706619
[patent_doc_number] => 10381067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Memory system topologies including a buffer device and an integrated circuit memory device
[patent_app_type] => utility
[patent_app_number] => 15/832468
[patent_app_country] => US
[patent_app_date] => 2017-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 61
[patent_no_of_words] => 26324
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832468
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/832468 | Memory system topologies including a buffer device and an integrated circuit memory device | Dec 4, 2017 | Issued |
Array
(
[id] => 12614640
[patent_doc_number] => 20180096710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => MEMORY DEVICE WITH STRAP CELLS
[patent_app_type] => utility
[patent_app_number] => 15/831332
[patent_app_country] => US
[patent_app_date] => 2017-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7780
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831332
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/831332 | Memory device with strap cells | Dec 3, 2017 | Issued |
Array
(
[id] => 12263551
[patent_doc_number] => 20180082748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'CONTROL CIRCUIT, PERIPHERAL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/825928
[patent_app_country] => US
[patent_app_date] => 2017-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11729
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825928
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/825928 | Semiconductor memory device and operation method for controlling bit line voltage of the same | Nov 28, 2017 | Issued |
Array
(
[id] => 14035991
[patent_doc_number] => 10229748
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-03-12
[patent_title] => Memory interface latch with integrated write-through function
[patent_app_type] => utility
[patent_app_number] => 15/823635
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8016
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823635
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/823635 | Memory interface latch with integrated write-through function | Nov 27, 2017 | Issued |
Array
(
[id] => 12263533
[patent_doc_number] => 20180082729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'Multilevel Ferroelectric Memory Cell for an Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 15/823230
[patent_app_country] => US
[patent_app_date] => 2017-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8572
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823230
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/823230 | Multilevel ferroelectric memory cell for an integrated circuit | Nov 26, 2017 | Issued |