Search

Vu Anh Le

Examiner (ID: 5206, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
0, 2818, 2511, 2825, 2824
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13098635 [patent_doc_number] => 10068660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Methods, apparatus, and system for global healing of write-limited die through bias temperature instability [patent_app_type] => utility [patent_app_number] => 15/615660 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7723 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615660
Methods, apparatus, and system for global healing of write-limited die through bias temperature instability Jun 5, 2017 Issued
Array ( [id] => 12553476 [patent_doc_number] => 10014047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Memory module supporting time-division memory access [patent_app_type] => utility [patent_app_number] => 15/610001 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/610001
Memory module supporting time-division memory access May 30, 2017 Issued
Array ( [id] => 12208319 [patent_doc_number] => 20180053545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/594891 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12606 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594891 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594891
Semiconductor memory devices, memory systems including the same and methods of operating the same May 14, 2017 Issued
Array ( [id] => 12181546 [patent_doc_number] => 20180040482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'Method Of Forming Low Height Split Gate Memory Cells' [patent_app_type] => utility [patent_app_number] => 15/594883 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2909 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594883
Method of forming low height split gate memory cells May 14, 2017 Issued
Array ( [id] => 11946141 [patent_doc_number] => 20170250292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/592588 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7461 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592588
Nonvolatile memory device May 10, 2017 Issued
Array ( [id] => 12375072 [patent_doc_number] => 09959916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Dual rail memory, memory macro and associated hybrid power supply method [patent_app_type] => utility [patent_app_number] => 15/589313 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589313
Dual rail memory, memory macro and associated hybrid power supply method May 7, 2017 Issued
Array ( [id] => 12047162 [patent_doc_number] => 09824770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Apparatuses and methods for flexible fuse transmission' [patent_app_type] => utility [patent_app_number] => 15/493772 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 11463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493772
Apparatuses and methods for flexible fuse transmission Apr 20, 2017 Issued
Array ( [id] => 11710233 [patent_doc_number] => 20170178732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY' [patent_app_type] => utility [patent_app_number] => 15/452537 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452537 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452537
Apparatuses and methods for charging a global access line prior to accessing a memory Mar 6, 2017 Issued
Array ( [id] => 11673510 [patent_doc_number] => 20170162232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'MEMORY DEVICE WITH STRAP CELLS' [patent_app_type] => utility [patent_app_number] => 15/438567 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438567 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438567
Memory device with strap cells Feb 20, 2017 Issued
Array ( [id] => 11861731 [patent_doc_number] => 09741419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Memory system with a content addressable superconducting memory' [patent_app_type] => utility [patent_app_number] => 15/437379 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437379 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437379
Memory system with a content addressable superconducting memory Feb 19, 2017 Issued
Array ( [id] => 11983391 [patent_doc_number] => 20170287546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/435383 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435383
Semiconductor memory devices and methods of operating the same Feb 16, 2017 Issued
Array ( [id] => 12497820 [patent_doc_number] => 09997229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Address decoder and active control circuit and semiconductor memory including the same [patent_app_type] => utility [patent_app_number] => 15/436495 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2260 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436495
Address decoder and active control circuit and semiconductor memory including the same Feb 16, 2017 Issued
Array ( [id] => 11911006 [patent_doc_number] => 09779824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'NAND flash memory comprising current sensing page buffer' [patent_app_type] => utility [patent_app_number] => 15/432147 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432147
NAND flash memory comprising current sensing page buffer Feb 13, 2017 Issued
Array ( [id] => 12631017 [patent_doc_number] => 20180102169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => DATA STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/427221 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427221
Data storage device and operating method thereof Feb 7, 2017 Issued
Array ( [id] => 11869296 [patent_doc_number] => 20170236581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'METHOD AND APPARATUS FOR READING RRAM CELL' [patent_app_type] => utility [patent_app_number] => 15/425213 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425213
Method and apparatus for reading RRAM cell Feb 5, 2017 Issued
Array ( [id] => 12114839 [patent_doc_number] => 09870833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Nonvolatile memory device including page buffer and method for verifying program operation thereof' [patent_app_type] => utility [patent_app_number] => 15/425557 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425557
Nonvolatile memory device including page buffer and method for verifying program operation thereof Feb 5, 2017 Issued
Array ( [id] => 12935326 [patent_doc_number] => 09830994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-28 [patent_title] => Sequential deselection of word lines for suppressing first read issue [patent_app_type] => utility [patent_app_number] => 15/422803 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 12467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15422803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/422803
Sequential deselection of word lines for suppressing first read issue Feb 1, 2017 Issued
Array ( [id] => 12101911 [patent_doc_number] => 09859008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Control circuit, peripheral circuit, semiconductor memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 15/421067 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11712 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421067
Control circuit, peripheral circuit, semiconductor memory device and method of operating the same Jan 30, 2017 Issued
Array ( [id] => 12047136 [patent_doc_number] => 09824744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'High-speed differential interface circuit with fast setup time' [patent_app_type] => utility [patent_app_number] => 15/418785 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5195 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15418785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/418785
High-speed differential interface circuit with fast setup time Jan 29, 2017 Issued
Array ( [id] => 12088907 [patent_doc_number] => 09842638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations' [patent_app_type] => utility [patent_app_number] => 15/414855 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19715 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414855
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations Jan 24, 2017 Issued
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