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Vu Anh Le

Examiner (ID: 12112, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2825, 2511, 0, 2824, 2818
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12088907 [patent_doc_number] => 09842638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations' [patent_app_type] => utility [patent_app_number] => 15/414855 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19715 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414855
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations Jan 24, 2017 Issued
Array ( [id] => 12088907 [patent_doc_number] => 09842638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations' [patent_app_type] => utility [patent_app_number] => 15/414855 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19715 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414855
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations Jan 24, 2017 Issued
Array ( [id] => 12088907 [patent_doc_number] => 09842638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations' [patent_app_type] => utility [patent_app_number] => 15/414855 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19715 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414855
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations Jan 24, 2017 Issued
Array ( [id] => 12012502 [patent_doc_number] => 09805822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Built-in self-test for adaptive delay-locked loop' [patent_app_type] => utility [patent_app_number] => 15/412093 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412093
Built-in self-test for adaptive delay-locked loop Jan 22, 2017 Issued
Array ( [id] => 11876209 [patent_doc_number] => 09747989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Memory device and control method thereof' [patent_app_type] => utility [patent_app_number] => 15/410815 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410815
Memory device and control method thereof Jan 19, 2017 Issued
Array ( [id] => 11592635 [patent_doc_number] => 20170117047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/397613 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397613
Semiconductor memory device Jan 2, 2017 Issued
Array ( [id] => 13018747 [patent_doc_number] => 10032488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => System and method of managing data in a non-volatile memory having a staging sub-drive [patent_app_type] => utility [patent_app_number] => 15/394311 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10486 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394311 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394311
System and method of managing data in a non-volatile memory having a staging sub-drive Dec 28, 2016 Issued
Array ( [id] => 12108842 [patent_doc_number] => 09865329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Memory system topologies including a buffer device and an integrated circuit memory device' [patent_app_type] => utility [patent_app_number] => 15/389409 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 61 [patent_no_of_words] => 28275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389409
Memory system topologies including a buffer device and an integrated circuit memory device Dec 21, 2016 Issued
Array ( [id] => 12256750 [patent_doc_number] => 09928899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)' [patent_app_type] => utility [patent_app_number] => 15/388991 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 18902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/388991
Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) Dec 21, 2016 Issued
Array ( [id] => 11967431 [patent_doc_number] => 20170271584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/387207 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7721 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387207
Semiconductor memory device and method for manufacturing the same Dec 20, 2016 Issued
Array ( [id] => 12012490 [patent_doc_number] => 09805810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Memory device with progressive row reading and related reading method' [patent_app_type] => utility [patent_app_number] => 15/387397 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387397
Memory device with progressive row reading and related reading method Dec 20, 2016 Issued
Array ( [id] => 12515586 [patent_doc_number] => 10002663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Nonvolatile memory apparatus and resistance compensation circuit thereof [patent_app_type] => utility [patent_app_number] => 15/382941 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8536 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382941 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382941
Nonvolatile memory apparatus and resistance compensation circuit thereof Dec 18, 2016 Issued
Array ( [id] => 12293940 [patent_doc_number] => 09935001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Methods of forming an integrated circuit chip having two types of memory cells [patent_app_type] => utility [patent_app_number] => 15/380936 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 12502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/380936
Methods of forming an integrated circuit chip having two types of memory cells Dec 14, 2016 Issued
Array ( [id] => 11672213 [patent_doc_number] => 20170160935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'CLOCK MODE DETERMINATION IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/378650 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14144 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378650 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378650
Clock mode determination in a memory system Dec 13, 2016 Issued
Array ( [id] => 12935251 [patent_doc_number] => 09830969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Multilevel ferroelectric memory cell for an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/367629 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8263 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367629
Multilevel ferroelectric memory cell for an integrated circuit Dec 1, 2016 Issued
Array ( [id] => 12229643 [patent_doc_number] => 09916889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Memory circuitry with row-wise gating capabilities' [patent_app_type] => utility [patent_app_number] => 15/366951 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5721 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366951
Memory circuitry with row-wise gating capabilities Nov 30, 2016 Issued
Array ( [id] => 11725017 [patent_doc_number] => 09697879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Memory device with shared read/write circuitry' [patent_app_type] => utility [patent_app_number] => 15/366083 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366083
Memory device with shared read/write circuitry Nov 30, 2016 Issued
Array ( [id] => 12334161 [patent_doc_number] => 09947387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Systems and methods for reducing standby power in floating body memory devices [patent_app_type] => utility [patent_app_number] => 15/361627 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12575 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361627
Systems and methods for reducing standby power in floating body memory devices Nov 27, 2016 Issued
Array ( [id] => 11890738 [patent_doc_number] => 09761300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Data shift apparatuses and methods' [patent_app_type] => utility [patent_app_number] => 15/358673 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 26755 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358673
Data shift apparatuses and methods Nov 21, 2016 Issued
Array ( [id] => 11665936 [patent_doc_number] => 20170154655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'STACKED MEMORY DEVICES, AND MEMORY PACKAGES AND MEMORY SYSTEMS HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/357041 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18372 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357041
Stacked memory devices, and memory packages and memory systems having the same Nov 20, 2016 Issued
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