Vu Anh Le

Array ( [id] => 18562749 [patent_doc_number] => 11727999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Zone swapping for wear leveling memory [patent_app_type] => utility [patent_app_number] => 17/697493 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18655354 [patent_doc_number] => 20230301212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => RERAM ANALOG PUF USING FILAMENT LOCATION [patent_app_type] => utility [patent_app_number] => 17/655184 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17886154 [patent_doc_number] => 20220301631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MULTIPLE TIME PROGRAMMABLE MEMORY USING ONE TIME PROGRAMMABLE MEMORY AND ERROR CORRECTION CODES [patent_app_type] => utility [patent_app_number] => 17/696475 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18781963 [patent_doc_number] => 11823728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Dynamic refresh rate control [patent_app_type] => utility [patent_app_number] => 17/687107 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168249 [patent_doc_number] => 11984160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Physical unclonable functions based on a circuit including resistive memory elements [patent_app_type] => utility [patent_app_number] => 17/679207 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19314203 [patent_doc_number] => 12040027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Memory system, memory controller, and semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/679761 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19314201 [patent_doc_number] => 12040025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Two-sided page scans with calibration feedback [patent_app_type] => utility [patent_app_number] => 17/675392 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18874407 [patent_doc_number] => 11862228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Power supply circuit and memory [patent_app_type] => utility [patent_app_number] => 17/668638 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168252 [patent_doc_number] => 11984163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Processing unit with fast read speed memory device [patent_app_type] => utility [patent_app_number] => 17/665123 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18967214 [patent_doc_number] => 11900992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Reference voltage adjustment for word line groups [patent_app_type] => utility [patent_app_number] => 17/649885 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 17244 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17900474 [patent_doc_number] => 20220310136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => DATA TRANSMISSION CIRCUIT AND METHOD, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/580757 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17582636 [patent_doc_number] => 20220139491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ELECTRONIC CHIP MEMORY [patent_app_type] => utility [patent_app_number] => 17/647793 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17566310 [patent_doc_number] => 20220130459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => FAST READ SPEED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/571094 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17630726 [patent_doc_number] => 20220165741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => THREE-DIMENSIONAL MEMORY AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/568639 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18507375 [patent_doc_number] => 11705199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Programming memory cells using asymmetric current pulses [patent_app_type] => utility [patent_app_number] => 17/567679 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18507371 [patent_doc_number] => 11705195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Increase of a sense current in memory [patent_app_type] => utility [patent_app_number] => 17/555005 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17508795 [patent_doc_number] => 20220101898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SYSTEMS AND METHODS INVOLVING WRITE TRAINING TO IMPROVE DATA VALID WINDOWS [patent_app_type] => utility [patent_app_number] => 17/545888 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19079258 [patent_doc_number] => 11948633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Resistive memory device and operating method of the resistive memory device [patent_app_type] => utility [patent_app_number] => 17/544543 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6609 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17485639 [patent_doc_number] => 20220093143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, MEMORY MODULE, AND METHOD OF OPERATING THE MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 17/541679 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18423685 [patent_doc_number] => 20230178149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => RESISTIVE MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/541168 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541168 [rel_patent_id] =>[rel_patent_doc_number] =>)