Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5246261 [patent_doc_number] => 20070242495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'PROGRAMMABLE READ-ONLY MEMORY' [patent_app_type] => utility [patent_app_number] => 11/733319 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242495.pdf [firstpage_image] =>[orig_patent_app_number] => 11733319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733319
Programmable read-only memory Apr 9, 2007 Issued
Array ( [id] => 276096 [patent_doc_number] => 07562271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Memory system topologies including a buffer device and an integrated circuit memory device' [patent_app_type] => utility [patent_app_number] => 11/697572 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 61 [patent_no_of_words] => 28103 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/562/07562271.pdf [firstpage_image] =>[orig_patent_app_number] => 11697572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697572
Memory system topologies including a buffer device and an integrated circuit memory device Apr 5, 2007 Issued
Array ( [id] => 906103 [patent_doc_number] => 07336553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Enhanced sensing in a hierarchical memory architecture' [patent_app_type] => utility [patent_app_number] => 11/697036 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336553.pdf [firstpage_image] =>[orig_patent_app_number] => 11697036 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697036
Enhanced sensing in a hierarchical memory architecture Apr 4, 2007 Issued
Array ( [id] => 4725577 [patent_doc_number] => 20080205118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/694393 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7525 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205118.pdf [firstpage_image] =>[orig_patent_app_number] => 11694393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694393
Integrated circuit having a resistive switching device Mar 29, 2007 Issued
Array ( [id] => 331505 [patent_doc_number] => 07512005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'NAND memory with side-tunneling' [patent_app_type] => utility [patent_app_number] => 11/693769 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7302 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512005.pdf [firstpage_image] =>[orig_patent_app_number] => 11693769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693769
NAND memory with side-tunneling Mar 29, 2007 Issued
Array ( [id] => 5507062 [patent_doc_number] => 20090080269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/917821 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9077 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080269.pdf [firstpage_image] =>[orig_patent_app_number] => 11917821 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/917821
Semiconductor memory device Mar 29, 2007 Issued
Array ( [id] => 4717257 [patent_doc_number] => 20080239779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'System and Method for Detecting Multiple Matches' [patent_app_type] => utility [patent_app_number] => 11/693441 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6538 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239779.pdf [firstpage_image] =>[orig_patent_app_number] => 11693441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693441
System and method for detecting multiple matches Mar 28, 2007 Issued
Array ( [id] => 4717291 [patent_doc_number] => 20080239813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method of Compensating Variations along a Word Line in a Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 11/693601 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239813.pdf [firstpage_image] =>[orig_patent_app_number] => 11693601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693601
Method of compensating variations along a word line in a non-volatile memory Mar 28, 2007 Issued
Array ( [id] => 906050 [patent_doc_number] => 07336535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/727693 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 58 [patent_no_of_words] => 18423 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336535.pdf [firstpage_image] =>[orig_patent_app_number] => 11727693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727693
Semiconductor integrated circuit device Mar 27, 2007 Issued
Array ( [id] => 248016 [patent_doc_number] => 07586773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Large array of upward pointing p-i-n diodes having large and uniform current' [patent_app_type] => utility [patent_app_number] => 11/692153 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7550 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/586/07586773.pdf [firstpage_image] =>[orig_patent_app_number] => 11692153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692153
Large array of upward pointing p-i-n diodes having large and uniform current Mar 26, 2007 Issued
11/688875 APPARATUS THAT ADJUSTS RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS Mar 20, 2007 Abandoned
Array ( [id] => 4937604 [patent_doc_number] => 20080074921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF OPERATING SAME' [patent_app_type] => utility [patent_app_number] => 11/689153 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074921.pdf [firstpage_image] =>[orig_patent_app_number] => 11689153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689153
Semiconductor integrated circuit device and method of operating same Mar 20, 2007 Issued
Array ( [id] => 4738518 [patent_doc_number] => 20080232170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/688949 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5082 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232170.pdf [firstpage_image] =>[orig_patent_app_number] => 11688949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688949
Memory device, a non-volatile semiconductor memory device and a method of forming a memory device Mar 20, 2007 Issued
Array ( [id] => 4741902 [patent_doc_number] => 20080235555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR RETENTION-TIME CONTROL AND ERROR MANAGEMENT IN A CACHE SYSTEM COMPRISING DYNAMIC STORAGE' [patent_app_type] => utility [patent_app_number] => 11/688455 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7529 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235555.pdf [firstpage_image] =>[orig_patent_app_number] => 11688455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688455
Retention-time control and error management in a cache system comprising dynamic storage Mar 19, 2007 Issued
Array ( [id] => 323680 [patent_doc_number] => 07518921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Semiconductor memory device which includes memory cell having charge accumulation layer and control gate' [patent_app_type] => utility [patent_app_number] => 11/688481 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13660 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518921.pdf [firstpage_image] =>[orig_patent_app_number] => 11688481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688481
Semiconductor memory device which includes memory cell having charge accumulation layer and control gate Mar 19, 2007 Issued
Array ( [id] => 4577093 [patent_doc_number] => 07848137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'MRAM and data read/write method for MRAM' [patent_app_type] => utility [patent_app_number] => 12/294397 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 11769 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/848/07848137.pdf [firstpage_image] =>[orig_patent_app_number] => 12294397 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/294397
MRAM and data read/write method for MRAM Mar 19, 2007 Issued
Array ( [id] => 279854 [patent_doc_number] => 07558932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Semiconductor memory device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 11/714665 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4994 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558932.pdf [firstpage_image] =>[orig_patent_app_number] => 11714665 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714665
Semiconductor memory device and method for operating the same Mar 5, 2007 Issued
Array ( [id] => 380692 [patent_doc_number] => 07310269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'High-speed verifiable semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/682741 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 11917 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310269.pdf [firstpage_image] =>[orig_patent_app_number] => 11682741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682741
High-speed verifiable semiconductor memory device Mar 5, 2007 Issued
Array ( [id] => 5006543 [patent_doc_number] => 20070204116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'MEMORY ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 11/679609 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4401 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204116.pdf [firstpage_image] =>[orig_patent_app_number] => 11679609 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679609
Memory arrangement Feb 26, 2007 Issued
Array ( [id] => 5111698 [patent_doc_number] => 20070195613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Memory module with memory stack and interface with enhanced capabilities' [patent_app_type] => utility [patent_app_number] => 11/702981 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11284 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195613.pdf [firstpage_image] =>[orig_patent_app_number] => 11702981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702981
Memory module with memory stack and interface with enhanced capabilities Feb 4, 2007 Issued
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