Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5078161 [patent_doc_number] => 20070121385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'PATTERN LAYOUT OF WORLD LINE TRANSFER TRANSISTORS IN NAND FLASH MEMORY WHICH EXECUTES SUBBLOCK ERASE' [patent_app_type] => utility [patent_app_number] => 11/627727 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121385.pdf [firstpage_image] =>[orig_patent_app_number] => 11627727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/627727
Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase Jan 25, 2007 Issued
Array ( [id] => 5235139 [patent_doc_number] => 20070127295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/657460 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14168 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20070127295.pdf [firstpage_image] =>[orig_patent_app_number] => 11657460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657460
Nonvolatile semiconductor memory Jan 24, 2007 Issued
Array ( [id] => 349849 [patent_doc_number] => 07495973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Circuit and method for controlling write recovery time in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/625597 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3615 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495973.pdf [firstpage_image] =>[orig_patent_app_number] => 11625597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625597
Circuit and method for controlling write recovery time in semiconductor memory device Jan 21, 2007 Issued
Array ( [id] => 5021191 [patent_doc_number] => 20070147157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Flash Card and Controller with Integrated Voltage Converter for Attachment to a Bus that can Operate at Either of Two Power-Supply Voltages' [patent_app_type] => utility [patent_app_number] => 11/625309 [patent_app_country] => US [patent_app_date] => 2007-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147157.pdf [firstpage_image] =>[orig_patent_app_number] => 11625309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625309
Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages Jan 19, 2007 Issued
Array ( [id] => 4763866 [patent_doc_number] => 20080175077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Novel write VCCMIN improvement scheme' [patent_app_type] => utility [patent_app_number] => 11/654983 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175077.pdf [firstpage_image] =>[orig_patent_app_number] => 11654983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654983
Write VCCMIN improvement scheme Jan 17, 2007 Issued
Array ( [id] => 5099935 [patent_doc_number] => 20070183196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Non-volatile memory device with periodic refresh and method of programming such a device' [patent_app_type] => utility [patent_app_number] => 11/654383 [patent_app_country] => US [patent_app_date] => 2007-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6410 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183196.pdf [firstpage_image] =>[orig_patent_app_number] => 11654383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654383
Non-volatile memory device with periodic refresh and method of programming such a device Jan 14, 2007 Issued
Array ( [id] => 243818 [patent_doc_number] => 07589555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Variable sized soft memory macros in structured cell arrays, and related methods' [patent_app_type] => utility [patent_app_number] => 11/651364 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4289 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589555.pdf [firstpage_image] =>[orig_patent_app_number] => 11651364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651364
Variable sized soft memory macros in structured cell arrays, and related methods Jan 7, 2007 Issued
Array ( [id] => 870828 [patent_doc_number] => 07366043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Current reduction circuit of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/620100 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4198 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366043.pdf [firstpage_image] =>[orig_patent_app_number] => 11620100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620100
Current reduction circuit of semiconductor device Jan 4, 2007 Issued
Array ( [id] => 16002 [patent_doc_number] => 07808818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Secondary injection for NROM' [patent_app_type] => utility [patent_app_number] => 11/646395 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 20845 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808818.pdf [firstpage_image] =>[orig_patent_app_number] => 11646395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646395
Secondary injection for NROM Dec 27, 2006 Issued
Array ( [id] => 572617 [patent_doc_number] => 07471577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Voltage generator and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/644895 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5891 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471577.pdf [firstpage_image] =>[orig_patent_app_number] => 11644895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644895
Voltage generator and methods thereof Dec 25, 2006 Issued
Array ( [id] => 4881803 [patent_doc_number] => 20080155186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Method and apparatus to program and erase a non-volatile static random access memory from the bit lines' [patent_app_type] => utility [patent_app_number] => 11/644641 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6621 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155186.pdf [firstpage_image] =>[orig_patent_app_number] => 11644641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644641
Method and apparatus to program and erase a non-volatile static random access memory from the bit lines Dec 21, 2006 Issued
Array ( [id] => 4878233 [patent_doc_number] => 20080151616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Method and apparatus to program both sides of a non-volatile static random access memory' [patent_app_type] => utility [patent_app_number] => 11/644819 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5565 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151616.pdf [firstpage_image] =>[orig_patent_app_number] => 11644819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644819
Method and apparatus to program both sides of a non-volatile static random access memory Dec 21, 2006 Issued
Array ( [id] => 5214930 [patent_doc_number] => 20070104010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory' [patent_app_type] => utility [patent_app_number] => 11/643689 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3667 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104010.pdf [firstpage_image] =>[orig_patent_app_number] => 11643689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643689
Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory Dec 21, 2006 Issued
Array ( [id] => 66439 [patent_doc_number] => 07760540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Combination SRAM and NVSRAM semiconductor memory array' [patent_app_type] => utility [patent_app_number] => 11/644789 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5284 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/760/07760540.pdf [firstpage_image] =>[orig_patent_app_number] => 11644789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644789
Combination SRAM and NVSRAM semiconductor memory array Dec 21, 2006 Issued
Array ( [id] => 338958 [patent_doc_number] => 07505303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Method and apparatus to create an erase disturb on a non-volatile static random access memory cell' [patent_app_type] => utility [patent_app_number] => 11/644447 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5355 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505303.pdf [firstpage_image] =>[orig_patent_app_number] => 11644447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644447
Method and apparatus to create an erase disturb on a non-volatile static random access memory cell Dec 21, 2006 Issued
Array ( [id] => 5134864 [patent_doc_number] => 20070076493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Circuit for generating data strobe signal of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/606928 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2863 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076493.pdf [firstpage_image] =>[orig_patent_app_number] => 11606928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606928
Circuit for generating data strobe signal of semiconductor memory device Nov 30, 2006 Issued
Array ( [id] => 5033211 [patent_doc_number] => 20070097750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'NAND FLASH MEMORY AND BLANK PAGE SEARCH METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/564887 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4421 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097750.pdf [firstpage_image] =>[orig_patent_app_number] => 11564887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564887
NAND flash memory and blank page search method therefor Nov 29, 2006 Issued
Array ( [id] => 4823172 [patent_doc_number] => 20080123427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'FLASH MEMORY, PROGRAM CIRCUIT AND PROGRAM METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/564077 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4516 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20080123427.pdf [firstpage_image] =>[orig_patent_app_number] => 11564077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564077
Flash memory, program circuit and program method thereof Nov 27, 2006 Issued
Array ( [id] => 293383 [patent_doc_number] => 07545681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Segmented bitscan for verification of programming' [patent_app_type] => utility [patent_app_number] => 11/563585 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 14195 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/545/07545681.pdf [firstpage_image] =>[orig_patent_app_number] => 11563585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563585
Segmented bitscan for verification of programming Nov 26, 2006 Issued
Array ( [id] => 811808 [patent_doc_number] => 07417905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory' [patent_app_type] => utility [patent_app_number] => 11/563213 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2511 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417905.pdf [firstpage_image] =>[orig_patent_app_number] => 11563213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563213
Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory Nov 26, 2006 Issued
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