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Array ( [id] => 482415 [patent_doc_number] => 07224633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'eFuse sense circuit' [patent_app_type] => utility [patent_app_number] => 11/297311 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224633.pdf [firstpage_image] =>[orig_patent_app_number] => 11297311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 507315 [patent_doc_number] => 07206223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'MRAM memory with residual write field reset' [patent_app_type] => utility [patent_app_number] => 11/297203 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 15105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206223.pdf [firstpage_image] =>[orig_patent_app_number] => 11297203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 568977 [patent_doc_number] => 07161850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'NAND flash memory and blank page search method therefor' [patent_app_type] => utility [patent_app_number] => 11/292347 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4212 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161850.pdf [firstpage_image] =>[orig_patent_app_number] => 11292347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7602634 [patent_doc_number] => 07236402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Method and apparatus for programming/erasing a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/290321 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236402.pdf [firstpage_image] =>[orig_patent_app_number] => 11290321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5078191 [patent_doc_number] => 20070121415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'PSEUDO-DYNAMIC WORD-LINE DRIVER' [patent_app_type] => utility [patent_app_number] => 11/290205 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121415.pdf [firstpage_image] =>[orig_patent_app_number] => 11290205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 433588 [patent_doc_number] => 07266010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Compact static memory cell with non-volatile storage capability' [patent_app_type] => utility [patent_app_number] => 11/288883 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7000 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266010.pdf [firstpage_image] =>[orig_patent_app_number] => 11288883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 445219 [patent_doc_number] => 07257045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Uni-stage delay speculative address decoder' [patent_app_type] => utility [patent_app_number] => 11/287907 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257045.pdf [firstpage_image] =>[orig_patent_app_number] => 11287907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5911351 [patent_doc_number] => 20060126413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Memory circuit and method for reading out a memory datum from such a memory circuit' [patent_app_type] => utility [patent_app_number] => 11/287501 [patent_app_country] => US [patent_app_date] => 2005-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20060126413.pdf [firstpage_image] =>[orig_patent_app_number] => 11287501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 405546 [patent_doc_number] => 07289381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-30 [patent_title] => 'Programmable boosting and charge neutralization' [patent_app_type] => utility [patent_app_number] => 11/285903 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5822 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/289/07289381.pdf [firstpage_image] =>[orig_patent_app_number] => 11285903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 144163 [patent_doc_number] => 07688624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/547905 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 56 [patent_no_of_words] => 21987 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688624.pdf [firstpage_image] =>[orig_patent_app_number] => 11547905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5647407 [patent_doc_number] => 20060133139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/283853 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133139.pdf [firstpage_image] =>[orig_patent_app_number] => 11283853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5647440 [patent_doc_number] => 20060133172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/283493 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2148 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133172.pdf [firstpage_image] =>[orig_patent_app_number] => 11283493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5725498 [patent_doc_number] => 20060056258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Semiconductor memory and method for operating the same' [patent_app_type] => utility [patent_app_number] => 11/265229 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15879 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20060056258.pdf [firstpage_image] =>[orig_patent_app_number] => 11265229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5758642 [patent_doc_number] => 20060209587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'High density memory device' [patent_app_type] => utility [patent_app_number] => 11/266776 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 69266 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20060209587.pdf [firstpage_image] =>[orig_patent_app_number] => 11266776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5033240 [patent_doc_number] => 20070097779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Generating a sampling clock signal in a communication block of a memory device' [patent_app_type] => utility [patent_app_number] => 11/264060 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10037 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097779.pdf [firstpage_image] =>[orig_patent_app_number] => 11264060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 895071 [patent_doc_number] => 07345915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Modified-layer EPROM cell' [patent_app_type] => utility [patent_app_number] => 11/263337 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4059 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345915.pdf [firstpage_image] =>[orig_patent_app_number] => 11263337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 846182 [patent_doc_number] => 07389392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Chip processors with integrated I/O' [patent_app_type] => utility [patent_app_number] => 11/262491 [patent_app_country] => US [patent_app_date] => 2005-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2762 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389392.pdf [firstpage_image] =>[orig_patent_app_number] => 11262491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5864366 [patent_doc_number] => 20060098496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method and apparatus for setting operational information of a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/259873 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11780 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20060098496.pdf [firstpage_image] =>[orig_patent_app_number] => 11259873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5806375 [patent_doc_number] => 20060092728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Circuit and method for test mode entry of a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/256357 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7137 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20060092728.pdf [firstpage_image] =>[orig_patent_app_number] => 11256357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 466993 [patent_doc_number] => 07239550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Method of programming a non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 11/255905 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2555 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239550.pdf [firstpage_image] =>[orig_patent_app_number] => 11255905 [rel_patent_id] =>[rel_patent_doc_number] =>)