Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 661166 [patent_doc_number] => 07106650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/034972 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5751 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106650.pdf [firstpage_image] =>[orig_patent_app_number] => 11034972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034972
Semiconductor memory device Jan 13, 2005 Issued
Array ( [id] => 7185306 [patent_doc_number] => 20050125595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/032165 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12293 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125595.pdf [firstpage_image] =>[orig_patent_app_number] => 11032165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032165
Non-volatile semiconductor memory Jan 10, 2005 Issued
Array ( [id] => 7044419 [patent_doc_number] => 20050249014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Multiple electrical fuss shared with one program device' [patent_app_type] => utility [patent_app_number] => 11/029431 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3404 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20050249014.pdf [firstpage_image] =>[orig_patent_app_number] => 11029431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029431
Multiple electrical fuses shared with one program device Jan 4, 2005 Issued
Array ( [id] => 5647436 [patent_doc_number] => 20060133168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor memory device for reducing chip area' [patent_app_type] => utility [patent_app_number] => 11/019675 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2500 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133168.pdf [firstpage_image] =>[orig_patent_app_number] => 11019675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019675
Semiconductor memory device for reducing chip area Dec 22, 2004 Issued
Array ( [id] => 5900503 [patent_doc_number] => 20060044865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 11/013429 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7222 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044865.pdf [firstpage_image] =>[orig_patent_app_number] => 11013429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/013429
Semiconductor storage device Dec 16, 2004 Issued
Array ( [id] => 7073680 [patent_doc_number] => 20050146947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/011427 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11771 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146947.pdf [firstpage_image] =>[orig_patent_app_number] => 11011427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/011427
Semiconductor device Dec 14, 2004 Issued
Array ( [id] => 6982125 [patent_doc_number] => 20050152194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'RAM memory circuit having a plurality of banks and an auxiliary device for testing' [patent_app_type] => utility [patent_app_number] => 11/012927 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20050152194.pdf [firstpage_image] =>[orig_patent_app_number] => 11012927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012927
RAM memory circuit having a plurality of banks and an auxiliary device for testing Dec 13, 2004 Issued
Array ( [id] => 6957037 [patent_doc_number] => 20050213407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Bit line sense amplifier for inhibiting increase of offset voltage and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/008231 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2329 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20050213407.pdf [firstpage_image] =>[orig_patent_app_number] => 11008231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008231
Bit line sense amplifier for inhibiting increase of offset voltage Dec 9, 2004 Issued
Array ( [id] => 7172313 [patent_doc_number] => 20050122765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Reference cell configuration for a 1T/1C ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/993202 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 19427 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122765.pdf [firstpage_image] =>[orig_patent_app_number] => 10993202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/993202
Reference cell configuration for a 1T/1C ferroelectric memory Nov 17, 2004 Abandoned
Array ( [id] => 6989853 [patent_doc_number] => 20050088890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages' [patent_app_type] => utility [patent_app_number] => 10/989318 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18125 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088890.pdf [firstpage_image] =>[orig_patent_app_number] => 10989318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989318
NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages Nov 16, 2004 Issued
Array ( [id] => 758745 [patent_doc_number] => 07020021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Ramped soft programming for control of erase voltage distributions in flash memory devices' [patent_app_type] => utility [patent_app_number] => 10/981833 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2901 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020021.pdf [firstpage_image] =>[orig_patent_app_number] => 10981833 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981833
Ramped soft programming for control of erase voltage distributions in flash memory devices Nov 3, 2004 Issued
Array ( [id] => 7010929 [patent_doc_number] => 20050064645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method of making adaptive negative differential resistance device' [patent_app_type] => utility [patent_app_number] => 10/979469 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22370 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064645.pdf [firstpage_image] =>[orig_patent_app_number] => 10979469 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979469
Method of making adaptive negative differential resistance device Oct 31, 2004 Issued
Array ( [id] => 7141709 [patent_doc_number] => 20050117377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Layout structure of bit line sense amplifier of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/977529 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4129 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20050117377.pdf [firstpage_image] =>[orig_patent_app_number] => 10977529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/977529
Layout structure of bit line sense amplifier of semiconductor memory device Oct 27, 2004 Issued
Array ( [id] => 7081848 [patent_doc_number] => 20050047228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method and system for selecting redundant rows and columns of memory cells' [patent_app_type] => utility [patent_app_number] => 10/966746 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10598 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047228.pdf [firstpage_image] =>[orig_patent_app_number] => 10966746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/966746
Method and system for selecting redundant rows and columns of memory cells Oct 14, 2004 Issued
Array ( [id] => 652266 [patent_doc_number] => 07113443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Method of address distribution time reduction for high speed memory macro' [patent_app_type] => utility [patent_app_number] => 10/965627 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113443.pdf [firstpage_image] =>[orig_patent_app_number] => 10965627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965627
Method of address distribution time reduction for high speed memory macro Oct 13, 2004 Issued
Array ( [id] => 936196 [patent_doc_number] => 06975546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Signal line driver circuit which reduces power consumption and enables high-speed data transfer' [patent_app_type] => utility [patent_app_number] => 10/960627 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 14388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975546.pdf [firstpage_image] =>[orig_patent_app_number] => 10960627 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960627
Signal line driver circuit which reduces power consumption and enables high-speed data transfer Oct 7, 2004 Issued
Array ( [id] => 780882 [patent_doc_number] => 06996000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Non-volatile ferroelectric SRAM' [patent_app_type] => utility [patent_app_number] => 10/961429 [patent_app_country] => US [patent_app_date] => 2004-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3905 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996000.pdf [firstpage_image] =>[orig_patent_app_number] => 10961429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/961429
Non-volatile ferroelectric SRAM Oct 6, 2004 Issued
Array ( [id] => 682484 [patent_doc_number] => 07085160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'NAND flash memory and blank page search method therefor' [patent_app_type] => utility [patent_app_number] => 10/958331 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4358 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085160.pdf [firstpage_image] =>[orig_patent_app_number] => 10958331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/958331
NAND flash memory and blank page search method therefor Oct 5, 2004 Issued
Array ( [id] => 710515 [patent_doc_number] => 07061806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Floating-body memory cell write' [patent_app_type] => utility [patent_app_number] => 10/954931 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2244 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061806.pdf [firstpage_image] =>[orig_patent_app_number] => 10954931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954931
Floating-body memory cell write Sep 29, 2004 Issued
Array ( [id] => 7156954 [patent_doc_number] => 20050083752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device' [patent_app_type] => utility [patent_app_number] => 10/950478 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4998 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083752.pdf [firstpage_image] =>[orig_patent_app_number] => 10950478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950478
Word line enable timing determination circuit of a memory device and methods of determining word line enable timing in the memory device Sep 27, 2004 Issued
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