Search

Vu Anh Le

Examiner (ID: 15321, Phone: (571)272-1871 , Office: P/2825 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2825, 0, 2824, 2511
Total Applications
2999
Issued Applications
2864
Pending Applications
54
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7204429 [patent_doc_number] => 20050052919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/658833 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052919.pdf [firstpage_image] =>[orig_patent_app_number] => 10658833 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658833
Temperature detecting circuit for controlling a self-refresh period of a semiconductor memory device Sep 8, 2003 Issued
Array ( [id] => 786466 [patent_doc_number] => 06990019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Nonvolatile semiconductor memory adapted to store a multi-valued data in a single memory cell' [patent_app_type] => utility [patent_app_number] => 10/656139 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 15454 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990019.pdf [firstpage_image] =>[orig_patent_app_number] => 10656139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/656139
Nonvolatile semiconductor memory adapted to store a multi-valued data in a single memory cell Sep 7, 2003 Issued
Array ( [id] => 7346788 [patent_doc_number] => 20040047228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Asynchronous hidden refresh of semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/656306 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6429 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20040047228.pdf [firstpage_image] =>[orig_patent_app_number] => 10656306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/656306
Asynchronous hidden refresh of semiconductor memory Sep 3, 2003 Issued
Array ( [id] => 486857 [patent_doc_number] => 07221580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'Memory gain cell' [patent_app_type] => utility [patent_app_number] => 10/648939 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2298 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221580.pdf [firstpage_image] =>[orig_patent_app_number] => 10648939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648939
Memory gain cell Aug 26, 2003 Issued
Array ( [id] => 7386179 [patent_doc_number] => 20040037126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Clock-synchronous semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/642624 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037126.pdf [firstpage_image] =>[orig_patent_app_number] => 10642624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642624
Clock-synchronous semiconductor memory device Aug 18, 2003 Issued
Array ( [id] => 947193 [patent_doc_number] => 06965528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Memory device having high bus efficiency of network, operating method of the same, and memory system including the same' [patent_app_type] => utility [patent_app_number] => 10/641637 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3058 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965528.pdf [firstpage_image] =>[orig_patent_app_number] => 10641637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641637
Memory device having high bus efficiency of network, operating method of the same, and memory system including the same Aug 13, 2003 Issued
Array ( [id] => 1032608 [patent_doc_number] => 06879511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Memory on a SOI substrate' [patent_app_type] => utility [patent_app_number] => 10/637233 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4513 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879511.pdf [firstpage_image] =>[orig_patent_app_number] => 10637233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637233
Memory on a SOI substrate Aug 7, 2003 Issued
Array ( [id] => 7374890 [patent_doc_number] => 20040027903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Control method of semiconductor memory device and semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/635431 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13097 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027903.pdf [firstpage_image] =>[orig_patent_app_number] => 10635431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635431
Control method of semiconductor memory device and semiconductor memory device Aug 6, 2003 Issued
Array ( [id] => 7225426 [patent_doc_number] => 20040156243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Circuit configuration for reading out a programmable link' [patent_app_type] => new [patent_app_number] => 10/627841 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4181 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156243.pdf [firstpage_image] =>[orig_patent_app_number] => 10627841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627841
Circuit configuration for reading out a programmable link Jul 24, 2003 Issued
Array ( [id] => 7136867 [patent_doc_number] => 20050181554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Semiconductor memory device and method for initializing the same' [patent_app_type] => utility [patent_app_number] => 10/515433 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5753 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181554.pdf [firstpage_image] =>[orig_patent_app_number] => 10515433 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/515433
Semiconductor memory device and method for initializing the same Jul 21, 2003 Issued
Array ( [id] => 1042092 [patent_doc_number] => 06870749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors' [patent_app_type] => utility [patent_app_number] => 10/619635 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 10572 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870749.pdf [firstpage_image] =>[orig_patent_app_number] => 10619635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619635
Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors Jul 14, 2003 Issued
Array ( [id] => 994835 [patent_doc_number] => 06917547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/616955 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5396 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917547.pdf [firstpage_image] =>[orig_patent_app_number] => 10616955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/616955
Non-volatile semiconductor memory device Jul 10, 2003 Issued
Array ( [id] => 1074599 [patent_doc_number] => 06839267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Structure and method of multiplexing bitline signals within a memory array' [patent_app_type] => utility [patent_app_number] => 10/618333 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839267.pdf [firstpage_image] =>[orig_patent_app_number] => 10618333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618333
Structure and method of multiplexing bitline signals within a memory array Jul 10, 2003 Issued
Array ( [id] => 7368087 [patent_doc_number] => 20040218456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/615237 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5786 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218456.pdf [firstpage_image] =>[orig_patent_app_number] => 10615237 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615237
Semiconductor memory device Jul 8, 2003 Issued
Array ( [id] => 1045386 [patent_doc_number] => 06868020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Synchronous semiconductor memory device having a desired-speed test mode' [patent_app_type] => utility [patent_app_number] => 10/614239 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4070 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868020.pdf [firstpage_image] =>[orig_patent_app_number] => 10614239 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614239
Synchronous semiconductor memory device having a desired-speed test mode Jul 7, 2003 Issued
Array ( [id] => 7421288 [patent_doc_number] => 20040160848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Cross point memory array with fast access time' [patent_app_type] => new [patent_app_number] => 10/612776 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9736 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160848.pdf [firstpage_image] =>[orig_patent_app_number] => 10612776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612776
Cross point memory array with fast access time Jun 30, 2003 Issued
Array ( [id] => 7421276 [patent_doc_number] => 20040160847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Layout of driver sets in a cross point memory array' [patent_app_type] => new [patent_app_number] => 10/612733 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9564 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160847.pdf [firstpage_image] =>[orig_patent_app_number] => 10612733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612733
Layout of driver sets in a cross point memory array Jun 30, 2003 Issued
Array ( [id] => 745527 [patent_doc_number] => 07031182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Rectifying charge storage memory circuit' [patent_app_type] => utility [patent_app_number] => 10/895429 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5594 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031182.pdf [firstpage_image] =>[orig_patent_app_number] => 10895429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895429
Rectifying charge storage memory circuit Jun 30, 2003 Issued
Array ( [id] => 1149552 [patent_doc_number] => 06778452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Circuit and method for voltage regulation in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/608060 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7388 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778452.pdf [firstpage_image] =>[orig_patent_app_number] => 10608060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608060
Circuit and method for voltage regulation in a semiconductor device Jun 26, 2003 Issued
Array ( [id] => 7457388 [patent_doc_number] => 20040165453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'MRAM having SAL layer' [patent_app_type] => new [patent_app_number] => 10/606733 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14804 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20040165453.pdf [firstpage_image] =>[orig_patent_app_number] => 10606733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606733
MRAM having SAL layer Jun 26, 2003 Issued
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